Module Name: src
Committed By: martin
Date: Sun Feb 2 14:51:59 UTC 2025
Modified Files:
src/sys/arch/x86/x86 [netbsd-10]: identcpu.c
Log Message:
Pull up following revision(s) (requested by andvar in ticket #1043):
sys/arch/x86/x86/identcpu.c: revision 1.132
sys/arch/x86/x86/identcpu.c: revision 1.133
Remove stepping check for APL30 Errata. Issue also affects newer Apollo Lake
CPUs. Therefore, the stepping check is unnecessary.
Include a reference to the errata and provide a description to clarify
the nature of the issue.
Should fix PR port-amd64/58982 reported by Wolfgang Stukenbrock.
x86/identcpu.c: Add archive link just in case.
Refill paragraph while here to avoid overlong lines.
To generate a diff of this commit:
cvs rdiff -u -r1.123.4.1 -r1.123.4.2 src/sys/arch/x86/x86/identcpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.123.4.1 src/sys/arch/x86/x86/identcpu.c:1.123.4.2
--- src/sys/arch/x86/x86/identcpu.c:1.123.4.1 Sat Jul 20 14:19:31 2024
+++ src/sys/arch/x86/x86/identcpu.c Sun Feb 2 14:51:59 2025
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.123.4.1 2024/07/20 14:19:31 martin Exp $ */
+/* $NetBSD: identcpu.c,v 1.123.4.2 2025/02/02 14:51:59 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.123.4.1 2024/07/20 14:19:31 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.123.4.2 2025/02/02 14:51:59 martin Exp $");
#include "opt_xen.h"
@@ -144,13 +144,27 @@ cpu_probe_intel_cache(struct cpu_info *c
static void
cpu_probe_intel_errata(struct cpu_info *ci)
{
- u_int family, model, stepping;
+ u_int family, model;
family = CPUID_TO_FAMILY(ci->ci_signature);
model = CPUID_TO_MODEL(ci->ci_signature);
- stepping = CPUID_TO_STEPPING(ci->ci_signature);
- if (family == 0x6 && model == 0x5C && stepping == 0x9) { /* Apollo Lake */
+ /*
+ * For details, refer to the Intel Pentium and Celeron Processor
+ * N- and J- Series Specification Update (Document number: 334820-010),
+ * August 2022, Revision 010. See page 28, Section 5.30: "APL30 A Store
+ * Instruction May Not Wake Up MWAIT."
+ * https://cdrdv2-public.intel.com/334820/334820-APL_Spec_Update_rev010.pdf
+ * https://web.archive.org/web/20250114072355/https://cdrdv2-public.intel.com/334820/334820-APL_Spec_Update_rev010.pdf
+ *
+ * Disable MWAIT/MONITOR on Apollo Lake CPUs to address the
+ * APL30 erratum. When using the MONITOR/MWAIT instruction
+ * pair, stores to the armed address range may fail to trigger
+ * MWAIT to resume execution. When these instructions are used
+ * to hatch secondary CPUs, this erratum causes SMP boot
+ * failures.
+ */
+ if (family == 0x6 && model == 0x5C) {
wrmsr(MSR_MISC_ENABLE,
rdmsr(MSR_MISC_ENABLE) & ~IA32_MISC_MWAIT_EN);
