Module Name: src Committed By: skrll Date: Thu Jan 2 12:31:46 UTC 2025
Modified Files:
src/sys/dev/fdt: dwiic_fdt.c
Log Message:
Fix previous with respect to the binding specification which I misread.
There must be 1 clocks (but there can be two) and the reset is optional.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/dev/fdt/dwiic_fdt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
