Module Name: src
Committed By: skrll
Date: Tue Dec 10 07:42:04 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: bus_dma.c
Log Message:
risc-v: bus_dma: Sprinkle error check with __predict_{true,false}.
Apply the same sprinkling of __predict_{true,false} to bus_dmamap_load*(),
and bus_dmamap_sync() that the arm version got to improve performance.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/riscv/bus_dma.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/bus_dma.c
diff -u src/sys/arch/riscv/riscv/bus_dma.c:1.8 src/sys/arch/riscv/riscv/bus_dma.c:1.9
--- src/sys/arch/riscv/riscv/bus_dma.c:1.8 Mon Oct 21 07:10:43 2024
+++ src/sys/arch/riscv/riscv/bus_dma.c Tue Dec 10 07:42:03 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma.c,v 1.8 2024/10/21 07:10:43 skrll Exp $ */
+/* $NetBSD: bus_dma.c,v 1.9 2024/12/10 07:42:03 skrll Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2020 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define _RISCV_NEED_BUS_DMA_BOUNCE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.8 2024/10/21 07:10:43 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.9 2024/12/10 07:42:03 skrll Exp $");
#include <sys/param.h>
@@ -210,7 +210,7 @@ _bus_dmamap_load_paddr(bus_dma_tag_t t,
/* XXX cache last result? */
const struct riscv_dma_range * const dr =
_bus_dma_paddr_inrange(t->_ranges, t->_nranges, paddr);
- if (dr == NULL) {
+ if (__predict_false(dr == NULL)) {
STAT_INCR(inrange_fail);
return EINVAL;
}
@@ -258,7 +258,7 @@ _bus_dmamap_load_paddr(bus_dma_tag_t t,
(segs[nseg - 1].ds_addr & bmask) == (curaddr & bmask))) {
/* coalesce */
segs[nseg - 1].ds_len += sgsize;
- } else if (nseg >= map->_dm_segcnt) {
+ } else if (__predict_false(nseg >= map->_dm_segcnt)) {
return EFBIG;
} else {
/* new segment */
@@ -305,7 +305,7 @@ _bus_dma_load_bouncebuf(bus_dma_tag_t t,
*/
if ((cookie->id_flags & _BUS_DMA_HAS_BOUNCE) == 0) {
error = _bus_dma_alloc_bouncebuf(t, map, buflen, flags);
- if (error)
+ if (__predict_false(error))
return error;
}
@@ -326,7 +326,7 @@ _bus_dma_load_bouncebuf(bus_dma_tag_t t,
cookie->id_origbuflen = buflen;
error = _bus_dmamap_load_buffer(t, map, cookie->id_bouncebuf,
buflen, vm, flags);
- if (error)
+ if (__predict_false(error))
return error;
STAT_INCR(bounced_loads);
@@ -540,7 +540,7 @@ _bus_dmamap_load(bus_dma_tag_t t, bus_dm
"dm_maxsegsz %" PRIuBUSSIZE " _dm_maxmaxsegsz %" PRIuBUSSIZE,
map->dm_maxsegsz, map->_dm_maxmaxsegsz);
- if (buflen > map->_dm_size)
+ if (__predict_false(buflen > map->_dm_size))
return EINVAL;
if (p != NULL) {
@@ -553,7 +553,7 @@ _bus_dmamap_load(bus_dma_tag_t t, bus_dm
map->_dm_flags |= _BUS_DMAMAP_COHERENT;
error = _bus_dmamap_load_buffer(t, map, buf, buflen, vm, flags);
- if (error == 0) {
+ if (__predict_true(error == 0)) {
map->dm_mapsize = buflen;
map->_dm_vmspace = vm;
map->_dm_origbuf = buf;
@@ -616,7 +616,7 @@ _bus_dmamap_load_mbuf(bus_dma_tag_t t, b
KASSERT(m0->m_flags & M_PKTHDR);
- if (m0->m_pkthdr.len > map->_dm_size)
+ if (__predict_false(m0->m_pkthdr.len > map->_dm_size))
return EINVAL;
/* _bus_dmamap_load_paddr() clears this if we're not... */
@@ -635,7 +635,7 @@ _bus_dmamap_load_mbuf(bus_dma_tag_t t, b
/*
* Don't allow reads in read-only mbufs.
*/
- if (M_ROMAP(m) && (flags & BUS_DMA_READ)) {
+ if (__predict_false(M_ROMAP(m) && (flags & BUS_DMA_READ))) {
error = EFAULT;
break;
}
@@ -676,7 +676,7 @@ _bus_dmamap_load_mbuf(bus_dma_tag_t t, b
error = _bus_dmamap_load_paddr(t, map,
paddr, size, false);
- if (error)
+ if (__predict_false(error))
break;
offset = 0;
remainbytes -= size;
@@ -696,7 +696,7 @@ _bus_dmamap_load_mbuf(bus_dma_tag_t t, b
m->m_len, vmspace_kernel(), flags);
}
}
- if (error == 0) {
+ if (__predict_true(error == 0)) {
map->dm_mapsize = m0->m_pkthdr.len;
map->_dm_origbuf = m0;
map->_dm_buftype = _BUS_DMA_BUFTYPE_MBUF;
@@ -760,7 +760,7 @@ _bus_dmamap_load_uio(bus_dma_tag_t t, bu
resid -= minlen;
}
- if (error == 0) {
+ if (__predict_true(error == 0)) {
map->dm_mapsize = uio->uio_resid;
map->_dm_origbuf = uio;
map->_dm_buftype = _BUS_DMA_BUFTYPE_UIO;
@@ -793,7 +793,7 @@ _bus_dmamap_load_raw(bus_dma_tag_t t, bu
map->dm_nsegs = 0;
KASSERT(map->dm_maxsegsz <= map->_dm_maxmaxsegsz);
- if (size0 > map->_dm_size)
+ if (__predict_false(size0 > map->_dm_size))
return EINVAL;
for (i = 0, size = size0; i < nsegs && size > 0; i++) {
@@ -807,12 +807,12 @@ _bus_dmamap_load_raw(bus_dma_tag_t t, bu
(ds->_ds_flags & _BUS_DMAMAP_COHERENT) != 0;
error = _bus_dmamap_load_paddr(t, map, ds->ds_addr,
sgsize, coherent);
- if (error != 0)
+ if (__predict_false(error != 0))
break;
size -= sgsize;
}
- if (error != 0) {
+ if (__predict_false(error != 0)) {
map->dm_mapsize = 0;
map->dm_nsegs = 0;
return error;
@@ -1077,9 +1077,9 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm
/*
* Mixing of PRE and POST operations is not allowed.
*/
- if ((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) != 0 &&
- (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)) != 0)
- panic("%s: mix PRE and POST", __func__);
+ KASSERTMSG((((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) == 0)
+ || ((ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)) == 0)),
+ "%s: mix PRE and POST", __func__);
KASSERTMSG(offset < map->dm_mapsize,
"offset %" PRIxBUSADDR " mapsize %" PRIuBUSSIZE,
@@ -1577,7 +1577,7 @@ _bus_dmamap_load_buffer(bus_dma_tag_t t,
error = _bus_dmamap_load_paddr(t, map, curaddr, sgsize,
false);
- if (error)
+ if (__predict_false(error))
return error;
vaddr += sgsize;
