Module Name: src
Committed By: andvar
Date: Mon Sep 23 18:52:55 UTC 2024
Modified Files:
src/sys/arch/arm/at91: at91twireg.h
Log Message:
s/hodling/holding/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/at91/at91twireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/at91/at91twireg.h
diff -u src/sys/arch/arm/at91/at91twireg.h:1.3 src/sys/arch/arm/at91/at91twireg.h:1.4
--- src/sys/arch/arm/at91/at91twireg.h:1.3 Sat May 6 21:37:37 2023
+++ src/sys/arch/arm/at91/at91twireg.h Mon Sep 23 18:52:55 2024
@@ -1,5 +1,5 @@
-/* $Id: at91twireg.h,v 1.3 2023/05/06 21:37:37 andvar Exp $ */
-/* $NetBSD: at91twireg.h,v 1.3 2023/05/06 21:37:37 andvar Exp $ */
+/* $Id: at91twireg.h,v 1.4 2024/09/23 18:52:55 andvar Exp $ */
+/* $NetBSD: at91twireg.h,v 1.4 2024/09/23 18:52:55 andvar Exp $ */
/*-
* Copyright (c) 2007 Embedtronics Oy.
@@ -82,7 +82,7 @@
#define TWI_SR_UNRE 0x080U /* 1 = underrun error */
#define TWI_SR_OVRE 0x040U /* 1 = overrun error */
#define TWI_SR_TXRDY 0x004U /* 1 = transmit holding reg rdy */
-#define TWI_SR_RXRDY 0x002U /* 1 = receive hodling reg rdy */
+#define TWI_SR_RXRDY 0x002U /* 1 = receive holding reg rdy */
#define TWI_SR_TXCOMP 0x001U /* 1 = transmission completed */
