Module Name: src
Committed By: skrll
Date: Tue Aug 13 07:20:23 UTC 2024
Modified Files:
src/sys/arch/arm/sunxi: sun6i_dma.c sunxi_gpio.c sunxi_gpio.h
sunxi_sid.c sunxi_usbphy.c
src/sys/arch/riscv/conf: GENERIC64 files.generic64 std.riscv
std.riscv64
Added Files:
src/sys/arch/riscv/sunxi: files.sunxi sun20i_d1_ccu.c sun20i_d1_ccu.h
sun20i_d1_gpio.c
Log Message:
risc-v: Allwinner D1 support
Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.
https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html
Only driver listed as attaching in
https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log
have been added.
There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/sunxi/sun6i_dma.c
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/sunxi/sunxi_gpio.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/sunxi/sunxi_gpio.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/sunxi/sunxi_sid.c
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/sunxi/sunxi_usbphy.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/conf/GENERIC64
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/conf/files.generic64
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/conf/std.riscv
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/conf/std.riscv64
cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/sunxi/files.sunxi \
src/sys/arch/riscv/sunxi/sun20i_d1_ccu.c \
src/sys/arch/riscv/sunxi/sun20i_d1_ccu.h \
src/sys/arch/riscv/sunxi/sun20i_d1_gpio.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/sunxi/sun6i_dma.c
diff -u src/sys/arch/arm/sunxi/sun6i_dma.c:1.15 src/sys/arch/arm/sunxi/sun6i_dma.c:1.16
--- src/sys/arch/arm/sunxi/sun6i_dma.c:1.15 Wed May 5 10:24:04 2021
+++ src/sys/arch/arm/sunxi/sun6i_dma.c Tue Aug 13 07:20:23 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sun6i_dma.c,v 1.15 2021/05/05 10:24:04 jmcneill Exp $ */
+/* $NetBSD: sun6i_dma.c,v 1.16 2024/08/13 07:20:23 skrll Exp $ */
/*-
* Copyright (c) 2014-2017 Jared McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
#include "opt_ddb.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sun6i_dma.c,v 1.15 2021/05/05 10:24:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sun6i_dma.c,v 1.16 2024/08/13 07:20:23 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -151,6 +151,16 @@ static const struct sun6idma_config sun8
.widths = WIDTHS_1_2_4,
};
+static const struct sun6idma_config sun20i_d1_dma_config = {
+ .num_channels = 16,
+ .autogate = true,
+ .autogate_reg = 0x28,
+ .autogate_mask = 0x4,
+ .burst_mask = __BITS(7,6),
+ .bursts = BURSTS_1_4_8_16,
+ .widths = WIDTHS_1_2_4_8,
+};
+
static const struct sun6idma_config sun50i_a64_dma_config = {
.num_channels = 8,
.autogate = true,
@@ -170,6 +180,8 @@ static const struct device_compatible_en
.data = &sun8i_h3_dma_config },
{ .compat = "allwinner,sun8i-v3s-dma",
.data = &sun8i_v3s_dma_config },
+ { .compat = "allwinner,sun20i-d1-dma",
+ .data = &sun20i_d1_dma_config },
{ .compat = "allwinner,sun50i-a64-dma",
.data = &sun50i_a64_dma_config },
Index: src/sys/arch/arm/sunxi/sunxi_gpio.c
diff -u src/sys/arch/arm/sunxi/sunxi_gpio.c:1.38 src/sys/arch/arm/sunxi/sunxi_gpio.c:1.39
--- src/sys/arch/arm/sunxi/sunxi_gpio.c:1.38 Tue Jun 28 05:19:03 2022
+++ src/sys/arch/arm/sunxi/sunxi_gpio.c Tue Aug 13 07:20:23 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_gpio.c,v 1.38 2022/06/28 05:19:03 skrll Exp $ */
+/* $NetBSD: sunxi_gpio.c,v 1.39 2024/08/13 07:20:23 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
#include "opt_soc.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.38 2022/06/28 05:19:03 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.39 2024/08/13 07:20:23 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -121,6 +121,10 @@ static const struct device_compatible_en
{ .compat = "allwinner,sun9i-a80-r-pinctrl",
.data = &sun9i_a80_r_padconf },
#endif
+#ifdef SOC_SUN20I_D1
+ { .compat = "allwinner,sun20i-d1-pinctrl",
+ .data = &sun20i_d1_padconf },
+#endif
#ifdef SOC_SUN50I_A64
{ .compat = "allwinner,sun50i-a64-pinctrl",
.data = &sun50i_a64_padconf },
Index: src/sys/arch/arm/sunxi/sunxi_gpio.h
diff -u src/sys/arch/arm/sunxi/sunxi_gpio.h:1.10 src/sys/arch/arm/sunxi/sunxi_gpio.h:1.11
--- src/sys/arch/arm/sunxi/sunxi_gpio.h:1.10 Tue Jun 28 05:19:03 2022
+++ src/sys/arch/arm/sunxi/sunxi_gpio.h Tue Aug 13 07:20:23 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_gpio.h,v 1.10 2022/06/28 05:19:03 skrll Exp $ */
+/* $NetBSD: sunxi_gpio.h,v 1.11 2024/08/13 07:20:23 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -34,7 +34,7 @@
#include "opt_soc.h"
-#define SUNXI_GPIO_MAXFUNC 8
+#define SUNXI_GPIO_MAXFUNC 15
struct sunxi_gpio_pins {
const char *name;
@@ -88,6 +88,10 @@ extern const struct sunxi_gpio_padconf s
extern const struct sunxi_gpio_padconf sun9i_a80_r_padconf;
#endif
+#ifdef SOC_SUN20I_D1
+extern const struct sunxi_gpio_padconf sun20i_d1_padconf;
+#endif
+
#ifdef SOC_SUN50I_A64
extern const struct sunxi_gpio_padconf sun50i_a64_padconf;
extern const struct sunxi_gpio_padconf sun50i_a64_r_padconf;
Index: src/sys/arch/arm/sunxi/sunxi_sid.c
diff -u src/sys/arch/arm/sunxi/sunxi_sid.c:1.7 src/sys/arch/arm/sunxi/sunxi_sid.c:1.8
--- src/sys/arch/arm/sunxi/sunxi_sid.c:1.7 Wed Jan 27 03:10:20 2021
+++ src/sys/arch/arm/sunxi/sunxi_sid.c Tue Aug 13 07:20:23 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_sid.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $ */
+/* $NetBSD: sunxi_sid.c,v 1.8 2024/08/13 07:20:23 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_sid.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_sid.c,v 1.8 2024/08/13 07:20:23 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -59,6 +59,7 @@ static const struct device_compatible_en
{ .compat = "allwinner,sun7i-a20-sid", .data = &sun4i_a10_sid_config },
{ .compat = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_sid_config },
{ .compat = "allwinner,sun8i-a83t-sid", .data = &sun8i_h3_sid_config },
+ { .compat = "allwinner,sun20i-d1-sid", .data = &sun8i_h3_sid_config },
{ .compat = "allwinner,sun50i-a64-sid", .data = &sun8i_h3_sid_config },
DEVICE_COMPAT_EOL
};
Index: src/sys/arch/arm/sunxi/sunxi_usbphy.c
diff -u src/sys/arch/arm/sunxi/sunxi_usbphy.c:1.17 src/sys/arch/arm/sunxi/sunxi_usbphy.c:1.18
--- src/sys/arch/arm/sunxi/sunxi_usbphy.c:1.17 Tue Jun 28 05:19:03 2022
+++ src/sys/arch/arm/sunxi/sunxi_usbphy.c Tue Aug 13 07:20:23 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_usbphy.c,v 1.17 2022/06/28 05:19:03 skrll Exp $ */
+/* $NetBSD: sunxi_usbphy.c,v 1.18 2024/08/13 07:20:23 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.17 2022/06/28 05:19:03 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.18 2024/08/13 07:20:23 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -80,6 +80,7 @@ enum sunxi_usbphy_type {
USBPHY_A31,
USBPHY_A64,
USBPHY_A83T,
+ USBPHY_D1,
USBPHY_H3,
USBPHY_H6,
};
@@ -92,6 +93,7 @@ static const struct device_compatible_en
{ .compat = "allwinner,sun8i-a83t-usb-phy", .value = USBPHY_A83T },
{ .compat = "allwinner,sun8i-h3-usb-phy", .value = USBPHY_H3 },
{ .compat = "allwinner,sun8i-v3s-usb-phy", .value = USBPHY_H3 },
+ { .compat = "allwinner,sun20i-d1-usb-phy", .value = USBPHY_D1 },
{ .compat = "allwinner,sun50i-a64-usb-phy", .value = USBPHY_A64 },
{ .compat = "allwinner,sun50i-h6-usb-phy", .value = USBPHY_H6 },
DEVICE_COMPAT_EOL
@@ -150,6 +152,7 @@ sunxi_usbphy_write(struct sunxi_usbphy_s
case USBPHY_A31:
reg = PHYCTL_A10;
break;
+ case USBPHY_D1:
case USBPHY_H3:
case USBPHY_H6:
case USBPHY_A64:
@@ -233,6 +236,7 @@ sunxi_usbphy_enable(device_t dev, void *
phy0_reroute = false;
break;
case USBPHY_A64:
+ case USBPHY_D1:
case USBPHY_H3:
case USBPHY_H6:
disc_thresh = 0x3;
Index: src/sys/arch/riscv/conf/GENERIC64
diff -u src/sys/arch/riscv/conf/GENERIC64:1.9 src/sys/arch/riscv/conf/GENERIC64:1.10
--- src/sys/arch/riscv/conf/GENERIC64:1.9 Fri Feb 9 08:51:49 2024
+++ src/sys/arch/riscv/conf/GENERIC64 Tue Aug 13 07:20:23 2024
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC64,v 1.9 2024/02/09 08:51:49 skrll Exp $
+# $NetBSD: GENERIC64,v 1.10 2024/08/13 07:20:23 skrll Exp $
#
# GENERIC machine description file
#
@@ -49,11 +49,23 @@ options DEBUG # expensive debugging ch
# Cache controller
ccache* at fdt? # SiFive FU[57]40 L2 Cache
-# Clock controller
+# Fixed Voltage/Current Regulators
+fregulator* at fdt? pass 4
+
+# Clock and reset controller
jh7100clkc* at fdt? pass 2 # StarFive JH7100 clock controller
+sun20id1ccu* at fdt? pass 2 # Allwinner D1/D1s CCU
+
+# Security ID EFUSE
+sunxisid* at fdt? pass 4 # Allwinner SID
+
+# DMA
+sun6idma* at fdt? pass 4 # Allwinner DMA controller (sun6i)
# Pin control
jh7100pinctrl* at fdt? pass 2 # StarFive JH7100 pinctrl driver
+sunxigpio* at fdt? pass 3 # Allwinner GPIO
+gpio* at gpiobus?
# SDMMC
dwcmmc* at fdt? # DesignWare SD/MMC
@@ -65,6 +77,9 @@ ld3 at sdmmc3
ld* at sdmmc?
bwfm* at sdmmc? # Broadcom BCM43xxx WiFi Interface
+# USB PHY
+sunxiusbphy* at fdt? # Allwinner USB PHY
+
# USB
jh71x0usb* at fdt? # StarFive JH71x0 usb
Index: src/sys/arch/riscv/conf/files.generic64
diff -u src/sys/arch/riscv/conf/files.generic64:1.2 src/sys/arch/riscv/conf/files.generic64:1.3
--- src/sys/arch/riscv/conf/files.generic64:1.2 Tue Jan 16 09:06:46 2024
+++ src/sys/arch/riscv/conf/files.generic64 Tue Aug 13 07:20:23 2024
@@ -1,4 +1,4 @@
-# $NetBSD: files.generic64,v 1.2 2024/01/16 09:06:46 skrll Exp $
+# $NetBSD: files.generic64,v 1.3 2024/08/13 07:20:23 skrll Exp $
#
# Generic (RV64) kernel configuration info
#
@@ -6,3 +6,4 @@
# Add other board / vendor files here
include "arch/riscv/sifive/files.sifive"
include "arch/riscv/starfive/files.starfive"
+include "arch/riscv/sunxi/files.sunxi"
Index: src/sys/arch/riscv/conf/std.riscv
diff -u src/sys/arch/riscv/conf/std.riscv:1.1 src/sys/arch/riscv/conf/std.riscv:1.2
--- src/sys/arch/riscv/conf/std.riscv:1.1 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/conf/std.riscv Tue Aug 13 07:20:23 2024
@@ -1,5 +1,5 @@
#
-# $NetBSD: std.riscv,v 1.1 2015/03/28 16:13:56 matt Exp $
+# $NetBSD: std.riscv,v 1.2 2024/08/13 07:20:23 skrll Exp $
#
machine riscv
@@ -8,6 +8,8 @@ include "conf/std"
options EXEC_ELF32
options EXEC_SCRIPT
+options SOC_SUN20I_D1
+
#no defflag COMPAT_09
#no defflag COMPAT_10
#no defflag COMPAT_11
Index: src/sys/arch/riscv/conf/std.riscv64
diff -u src/sys/arch/riscv/conf/std.riscv64:1.3 src/sys/arch/riscv/conf/std.riscv64:1.4
--- src/sys/arch/riscv/conf/std.riscv64:1.3 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/conf/std.riscv64 Tue Aug 13 07:20:23 2024
@@ -1,5 +1,5 @@
#
-# $NetBSD: std.riscv64,v 1.3 2023/05/07 12:41:48 skrll Exp $
+# $NetBSD: std.riscv64,v 1.4 2024/08/13 07:20:23 skrll Exp $
#
machine riscv
@@ -8,6 +8,8 @@ include "conf/std"
options EXEC_SCRIPT
options EXEC_ELF64
+options SOC_SUN20I_D1
+
makeoptions LP64="yes"
#no defflag COMPAT_09
Added files:
Index: src/sys/arch/riscv/sunxi/files.sunxi
diff -u /dev/null src/sys/arch/riscv/sunxi/files.sunxi:1.1
--- /dev/null Tue Aug 13 07:20:23 2024
+++ src/sys/arch/riscv/sunxi/files.sunxi Tue Aug 13 07:20:23 2024
@@ -0,0 +1,50 @@
+# $NetBSD: files.sunxi,v 1.1 2024/08/13 07:20:23 skrll Exp $
+#
+# Configuration info for Allwinner sunxi family SoCs
+#
+#
+
+# CCU
+define sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_div.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_fixed_factor.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_fractional.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_gate.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_mux.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_nm.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_nkmp.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_phase.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_prediv.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_display.c sunxi_ccu
+
+# CCU (D1/D1s)
+device sun20id1ccu: sunxi_ccu
+attach sun20id1ccu at fdt with sunxi_d1_ccu
+file arch/riscv/sunxi/sun20i_d1_ccu.c sunxi_d1_ccu
+
+# GPIO
+device sunxigpio: gpiobus
+attach sunxigpio at fdt with sunxi_gpio
+file arch/arm/sunxi/sunxi_gpio.c sunxi_gpio
+file arch/riscv/sunxi/sun20i_d1_gpio.c sunxi_gpio & soc_sun20i_d1
+
+# DMA controller (sun6i)
+device sun6idma
+attach sun6idma at fdt with sun6i_dma
+file arch/arm/sunxi/sun6i_dma.c sun6i_dma
+
+# Security ID EFUSE
+device sunxisid
+attach sunxisid at fdt with sunxi_sid
+file arch/arm/sunxi/sunxi_sid.c sunxi_sid
+
+# USB PHY
+device sunxiusbphy
+attach sunxiusbphy at fdt with sunxi_usbphy
+file arch/arm/sunxi/sunxi_usbphy.c sunxi_usbphy
+
+# SOC parameters
+defflag opt_soc.h SOC_SUNXI
+defflag opt_soc.h SOC_SUN20I: SOC_SUNXI
+defflag opt_soc.h SOC_SUN20I_D1: SOC_SUN20I
Index: src/sys/arch/riscv/sunxi/sun20i_d1_ccu.c
diff -u /dev/null src/sys/arch/riscv/sunxi/sun20i_d1_ccu.c:1.1
--- /dev/null Tue Aug 13 07:20:23 2024
+++ src/sys/arch/riscv/sunxi/sun20i_d1_ccu.c Tue Aug 13 07:20:23 2024
@@ -0,0 +1,550 @@
+/* $NetBSD: sun20i_d1_ccu.c,v 1.1 2024/08/13 07:20:23 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2024 Rui-Xiang Guo
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun20i_d1_ccu.c,v 1.1 2024/08/13 07:20:23 skrll Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <riscv/sunxi/sun20i_d1_ccu.h>
+
+#define PLL_CPU_CTRL_REG 0x000
+#define PLL_DDR_CTRL_REG 0x010
+#define PLL_PERI_CTRL_REG 0x020
+#define PLL_AUDIO1_CTRL_REG 0x080
+#define PSI_CLK_REG 0x510
+#define APB0_CLK_REG 0x520
+#define APB1_CLK_REG 0x524
+#define MBUS_CLK_REG 0x540
+#define DE_BGR_REG 0x60c
+#define DI_BGR_REG 0x62c
+#define G2D_BGR_REG 0x63c
+#define CE_BGR_REG 0x68c
+#define VE_BGR_REG 0x69c
+#define DMA_BGR_REG 0x70c
+#define MSGBOX_BGR_REG 0x71c
+#define SPINLOCK_BGR_REG 0x72c
+#define HSTIMER_BGR_REG 0x73c
+#define AVS_CLK_REG 0x740
+#define DBGSYS_BGR_REG 0x78c
+#define PWM_BGR_REG 0x7ac
+#define IOMMU_BGR_REG 0x7bc
+#define DRAM_CLK_REG 0x800
+#define MBUS_MAT_CLK_GATING_REG 0x804
+#define DRAM_BGR_REG 0x80c
+#define SMHC0_CLK_REG 0x830
+#define SMHC1_CLK_REG 0x834
+#define SMHC2_CLK_REG 0x838
+#define SMHC_BGR_REG 0x84c
+#define UART_BGR_REG 0x90c
+#define TWI_BGR_REG 0x91c
+#define SPI_BGR_REG 0x96c
+#define EMAC_BGR_REG 0x97c
+#define IRTX_BGR_REG 0x9cc
+#define GPADC_BGR_REG 0x9ec
+#define THS_BGR_REG 0x9fc
+#define I2S_BGR_REG 0xa20
+#define OWA_BGR_REG 0xa2c
+#define DMIC_BGR_REG 0xa4c
+#define AUDIO_CODEC_BGR_REG 0xa5c
+#define USB0_CLK_REG 0xa70
+#define USB1_CLK_REG 0xa74
+#define USB_BGR_REG 0xa8c
+#define LRADC_BGR_REG 0xa9c
+#define DPSS_TOP_BGR_REG 0xabc
+#define HDMI_BGR_REG 0xb1c
+#define DSI_BGR_REG 0xb4c
+#define TCONLCD_BGR_REG 0xb7c
+#define TCONTV_BGR_REG 0xb9c
+#define LVDS_BGR_REG 0xbac
+#define TVE_BGR_REG 0xbbc
+#define TVD_BGR_REG 0xbdc
+#define LEDC_BGR_REG 0xbfc
+#define CSI_BGR_REG 0xc1c
+#define TPADC_BGR_REG 0xc5c
+#define DSP_BGR_REG 0xc7c
+#define RISCV_CFG_BGR_REG 0xd0c
+
+static int sun20i_d1_ccu_match(device_t, cfdata_t, void *);
+static void sun20i_d1_ccu_attach(device_t, device_t, void *);
+
+static const struct device_compatible_entry compat_data[] = {
+ { .compat = "allwinner,sun20i-d1-ccu" },
+ DEVICE_COMPAT_EOL
+};
+
+CFATTACH_DECL_NEW(sunxi_d1_ccu, sizeof(struct sunxi_ccu_softc),
+ sun20i_d1_ccu_match, sun20i_d1_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun20i_d1_ccu_resets[] = {
+ SUNXI_CCU_RESET(D1_RST_MBUS, MBUS_CLK_REG, 30),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_DE, DE_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_DI, DI_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_G2D, G2D_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_CE, CE_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_VE, VE_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_DMA, DMA_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX0, MSGBOX_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX1, MSGBOX_BGR_REG, 17),
+ SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX2, MSGBOX_BGR_REG, 18),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_SPINLOCK, SPINLOCK_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_HSTIMER, HSTIMER_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_DBGSYS, DBGSYS_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_PWM, PWM_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_DRAM, DRAM_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_MMC0, SMHC_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_MMC1, SMHC_BGR_REG, 17),
+ SUNXI_CCU_RESET(D1_RST_BUS_MMC2, SMHC_BGR_REG, 18),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_UART0, UART_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_UART1, UART_BGR_REG, 17),
+ SUNXI_CCU_RESET(D1_RST_BUS_UART2, UART_BGR_REG, 18),
+ SUNXI_CCU_RESET(D1_RST_BUS_UART3, UART_BGR_REG, 19),
+ SUNXI_CCU_RESET(D1_RST_BUS_UART4, UART_BGR_REG, 20),
+ SUNXI_CCU_RESET(D1_RST_BUS_UART5, UART_BGR_REG, 21),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_I2C0, TWI_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_I2C1, TWI_BGR_REG, 17),
+ SUNXI_CCU_RESET(D1_RST_BUS_I2C2, TWI_BGR_REG, 18),
+ SUNXI_CCU_RESET(D1_RST_BUS_I2C3, TWI_BGR_REG, 19),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_SPI0, SPI_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_SPI1, SPI_BGR_REG, 17),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_EMAC, EMAC_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_IRTX, IRTX_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_GPADC, GPADC_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_THS, THS_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_I2S0, I2S_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_I2S1, I2S_BGR_REG, 17),
+ SUNXI_CCU_RESET(D1_RST_BUS_I2S2, I2S_BGR_REG, 18),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_SPDIF, OWA_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_DMIC, DMIC_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_AUDIO, AUDIO_CODEC_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_USB_PHY0, USB0_CLK_REG, 30),
+
+ SUNXI_CCU_RESET(D1_RST_USB_PHY1, USB1_CLK_REG, 30),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_OHCI0, USB_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_OHCI1, USB_BGR_REG, 17),
+ SUNXI_CCU_RESET(D1_RST_BUS_EHCI0, USB_BGR_REG, 20),
+ SUNXI_CCU_RESET(D1_RST_BUS_EHCI1, USB_BGR_REG, 21),
+ SUNXI_CCU_RESET(D1_RST_BUS_OTG, USB_BGR_REG, 24),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_LRADC, LRADC_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_DPSS_TOP, DPSS_TOP_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_HDMI_SUB, HDMI_BGR_REG, 17),
+ SUNXI_CCU_RESET(D1_RST_BUS_HDMI_MAIN, HDMI_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_DSI, DSI_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_TCONLCD, TCONLCD_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_TCONTV, TCONTV_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_LVDS, LVDS_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_TVE_TOP, TVE_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_TVE, TVE_BGR_REG, 17),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_TVD_TOP, TVD_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_TVD, TVD_BGR_REG, 17),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_LEDC, LEDC_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_CSI, CSI_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_TPADC, TPADC_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_DSP, DSP_BGR_REG, 16),
+ SUNXI_CCU_RESET(D1_RST_BUS_DSP_CFG, DSP_BGR_REG, 17),
+ SUNXI_CCU_RESET(D1_RST_BUS_DSP_DBG, DSP_BGR_REG, 18),
+
+ SUNXI_CCU_RESET(D1_RST_BUS_RISCV_CFG, RISCV_CFG_BGR_REG, 16),
+};
+
+static const char *psi_parents[] = { "hosc", "losc", "iosc", "pll_periph" };
+static const char *apb_parents[] = { "hosc", "losc", "psi", "pll_periph" };
+static const char *dram_parents[] = { "pll_ddr", "pll_audio1_div2", "pll_periph_2x", "pll_periph_800m" };
+static const char *mmc_parents[] = { "hosc", "pll_periph", "pll_periph_2x", "pll_audio1_div2" };
+static const char *mmc2_parents[] = { "pll_periph", "pll_periph_2x", "pll_periph_800m", "pll_audio1_div2" };
+
+static struct sunxi_ccu_clk sun20i_d1_ccu_clks[] = {
+ SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_CPU, "pll_cpu", "hosc",
+ PLL_CPU_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ 0, /* k */
+ 0, /* m */
+ 0, /* p */
+ __BIT(31), /* enable */
+ __BIT(28), /* lock */
+ NULL, /* table */
+ SUNXI_CCU_NKMP_SCALE_CLOCK),
+
+ SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_DDR, "pll_ddr", "hosc",
+ PLL_DDR_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ 0, /* k */
+ __BIT(1), /* m */
+ __BIT(0), /* p */
+ __BIT(31), /* enable */
+ __BIT(28), /* lock */
+ NULL, /* table */
+ SUNXI_CCU_NKMP_SCALE_CLOCK),
+
+ SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_PERIPH_2X, "pll_periph_2x", "hosc",
+ PLL_PERI_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ 0, /* k */
+ __BIT(1), /* m */
+ __BITS(18,16), /* p */
+ __BIT(31), /* enable */
+ __BIT(28), /* lock */
+ NULL, /* table */
+ SUNXI_CCU_NKMP_SCALE_CLOCK),
+
+ SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_PERIPH_800M, "pll_periph_800m", "hosc",
+ PLL_PERI_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ 0, /* k */
+ __BIT(1), /* m */
+ __BITS(22,20), /* p */
+ __BIT(31), /* enable */
+ __BIT(28), /* lock */
+ NULL, /* table */
+ SUNXI_CCU_NKMP_SCALE_CLOCK),
+
+ SUNXI_CCU_FIXED_FACTOR(D1_CLK_PLL_PERIPH, "pll_periph", "pll_periph_2x", 2, 1),
+
+ SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_AUDIO1, "pll_audio1_div2", "hosc",
+ PLL_AUDIO1_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ 0, /* k */
+ __BIT(1), /* m */
+ __BITS(18,16), /* p */
+ __BIT(31), /* enable */
+ __BIT(28), /* lock */
+ NULL, /* table */
+ SUNXI_CCU_NKMP_SCALE_CLOCK),
+
+ SUNXI_CCU_NM(D1_CLK_PSI, "psi", psi_parents,
+ PSI_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(1,0), /* m */
+ __BITS(25,24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+
+ SUNXI_CCU_NM(D1_CLK_APB0, "apb0", apb_parents,
+ APB0_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(4,0), /* m */
+ __BITS(25,24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+
+ SUNXI_CCU_NM(D1_CLK_APB1, "apb1", apb_parents,
+ APB1_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(4,0), /* m */
+ __BITS(25,24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+
+ SUNXI_CCU_FIXED_FACTOR(D1_CLK_MBUS, "mbus", "dram", 4, 1),
+
+ SUNXI_CCU_NM(D1_CLK_DRAM, "dram", dram_parents,
+ DRAM_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(1,0), /* m */
+ __BITS(26,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+
+ SUNXI_CCU_NM(D1_CLK_MMC0, "mmc0", mmc_parents,
+ SMHC0_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(3,0), /* m */
+ __BITS(26,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_NM(D1_CLK_MMC1, "mmc1", mmc_parents,
+ SMHC1_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(3,0), /* m */
+ __BITS(26,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_NM(D1_CLK_MMC2, "mmc2", mmc2_parents,
+ SMHC2_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(3,0), /* m */
+ __BITS(26,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_DE, "bus-de", "psi",
+ DE_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_DI, "bus-di", "psi",
+ DI_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_G2D, "bus-g2d", "psi",
+ G2D_BGR_REG ,0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_CE, "bus-ce", "psi",
+ CE_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_VE, "bus-ve", "psi",
+ VE_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_DMA, "bus-dma", "psi",
+ DMA_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX0, "bus-msgbox0", "psi",
+ MSGBOX_BGR_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX1, "bus-msgbox1", "psi",
+ MSGBOX_BGR_REG, 1),
+ SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX2, "bus-msgbox2", "psi",
+ MSGBOX_BGR_REG, 2),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_SPINLOCK, "bus-spinlock", "psi",
+ SPINLOCK_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_HSTIMER, "bus-hstimer", "psi",
+ HSTIMER_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_AVS, "avs", "hosc",
+ AVS_CLK_REG, 31),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_DBGSYS, "bus-dbgsys", "psi",
+ DBGSYS_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_PWM, "bus-pwm", "apb0",
+ PWM_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_IOMMU, "bus-iommu", "apb0",
+ IOMMU_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_MBUS_DMA, "mbus-dma", "mbus",
+ MBUS_MAT_CLK_GATING_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_MBUS_VE, "mbus-ve", "mbus",
+ MBUS_MAT_CLK_GATING_REG, 1),
+ SUNXI_CCU_GATE(D1_CLK_MBUS_CE, "mbus-ce", "mbus",
+ MBUS_MAT_CLK_GATING_REG, 2),
+ SUNXI_CCU_GATE(D1_CLK_MBUS_TVIN, "mbus-tvin", "mbus",
+ MBUS_MAT_CLK_GATING_REG, 7),
+ SUNXI_CCU_GATE(D1_CLK_MBUS_CSI, "mbus-csi", "mbus",
+ MBUS_MAT_CLK_GATING_REG, 8),
+ SUNXI_CCU_GATE(D1_CLK_MBUS_G2D, "mbus-g2d", "mbus",
+ MBUS_MAT_CLK_GATING_REG, 10),
+ SUNXI_CCU_GATE(D1_CLK_MBUS_RISCV, "mbus-riscv", "mbus",
+ MBUS_MAT_CLK_GATING_REG, 11),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_DRAM, "bus-dram", "psi",
+ DRAM_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_MMC0, "bus-mmc0", "psi",
+ SMHC_BGR_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_BUS_MMC1, "bus-mmc1", "psi",
+ SMHC_BGR_REG, 1),
+ SUNXI_CCU_GATE(D1_CLK_BUS_MMC2, "bus-mmc2", "psi",
+ SMHC_BGR_REG, 2),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_UART0, "bus-uart0", "apb1",
+ UART_BGR_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_BUS_UART1, "bus-uart1", "apb1",
+ UART_BGR_REG, 1),
+ SUNXI_CCU_GATE(D1_CLK_BUS_UART2, "bus-uart2", "apb1",
+ UART_BGR_REG, 2),
+ SUNXI_CCU_GATE(D1_CLK_BUS_UART3, "bus-uart3", "apb1",
+ UART_BGR_REG, 3),
+ SUNXI_CCU_GATE(D1_CLK_BUS_UART4, "bus-uart4", "apb1",
+ UART_BGR_REG, 4),
+ SUNXI_CCU_GATE(D1_CLK_BUS_UART5, "bus-uart5", "apb1",
+ UART_BGR_REG, 5),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_I2C0, "bus-i2c0", "apb1",
+ TWI_BGR_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_BUS_I2C1, "bus-i2c1", "apb1",
+ TWI_BGR_REG, 1),
+ SUNXI_CCU_GATE(D1_CLK_BUS_I2C2, "bus-i2c2", "apb1",
+ TWI_BGR_REG, 2),
+ SUNXI_CCU_GATE(D1_CLK_BUS_I2C3, "bus-i2c3", "apb1",
+ TWI_BGR_REG, 3),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_SPI0, "bus-spi0", "psi",
+ SPI_BGR_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_BUS_SPI1, "bus-spi1", "psi",
+ SPI_BGR_REG, 1),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_EMAC, "bus-emac", "psi",
+ EMAC_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_IRTX, "bus-irtx", "apb0",
+ IRTX_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_GPADC, "bus-gpadc", "apb0",
+ GPADC_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_THS, "bus-ths", "apb0",
+ THS_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_I2S0, "bus-i2s0", "apb0",
+ I2S_BGR_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_BUS_I2S1, "bus-i2s1", "apb0",
+ I2S_BGR_REG, 1),
+ SUNXI_CCU_GATE(D1_CLK_BUS_I2S2, "bus-i2s2", "apb0",
+ I2S_BGR_REG, 2),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_SPDIF, "bus-spdif", "apb0",
+ OWA_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_DMIC, "bus-dmic", "apb0",
+ DMIC_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_AUDIO, "bus-audio", "apb0",
+ AUDIO_CODEC_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_OHCI0, "bus-ohci0", "psi",
+ USB_BGR_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_BUS_OHCI1, "bus-ohci1", "psi",
+ USB_BGR_REG, 1),
+ SUNXI_CCU_GATE(D1_CLK_BUS_EHCI0, "bus-ehci0", "psi",
+ USB_BGR_REG, 4),
+ SUNXI_CCU_GATE(D1_CLK_BUS_EHCI1, "bus-ehci1", "psi",
+ USB_BGR_REG, 5),
+ SUNXI_CCU_GATE(D1_CLK_BUS_OTG, "bus-otg", "psi",
+ USB_BGR_REG, 8),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_LRADC, "bus-lradc", "apb0",
+ LRADC_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_DPSS_TOP, "bus-dpss-top", "psi",
+ DPSS_TOP_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_HDMI, "bus-hdmi", "psi",
+ HDMI_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_DSI, "bus-dsi", "psi",
+ DSI_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_TCONLCD, "bus-tconlcd", "psi",
+ TCONLCD_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_TCONTV, "bus-tcontv", "psi",
+ TCONTV_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_TVE_TOP, "bus-tve-top", "psi",
+ TVE_BGR_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_BUS_TVE, "bus-tve", "psi",
+ TVE_BGR_REG, 1),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_TVD_TOP, "bus-tvd-top", "psi",
+ TVD_BGR_REG, 0),
+ SUNXI_CCU_GATE(D1_CLK_BUS_TVD, "bus-tvd", "psi",
+ TVD_BGR_REG, 1),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_LEDC, "bus-ledc", "psi",
+ LEDC_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_CSI, "bus-csi", "psi",
+ CSI_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_TPADC, "bus-tpadc", "apb0",
+ TPADC_BGR_REG, 0),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_DSP_CFG, "bus-dsp-cfg", "psi",
+ DSP_BGR_REG, 1),
+
+ SUNXI_CCU_GATE(D1_CLK_BUS_RISCV_CFG, "bus-riscv-cfg", "psi",
+ RISCV_CFG_BGR_REG, 0),
+};
+
+static int
+sun20i_d1_ccu_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_compatible_match(faa->faa_phandle, compat_data);
+}
+
+static void
+sun20i_d1_ccu_attach(device_t parent, device_t self, void *aux)
+{
+ struct sunxi_ccu_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = faa->faa_phandle;
+ sc->sc_bst = faa->faa_bst;
+
+ sc->sc_resets = sun20i_d1_ccu_resets;
+ sc->sc_nresets = __arraycount(sun20i_d1_ccu_resets);
+
+ sc->sc_clks = sun20i_d1_ccu_clks;
+ sc->sc_nclks = __arraycount(sun20i_d1_ccu_clks);
+
+ if (sunxi_ccu_attach(sc) != 0)
+ return;
+
+ aprint_naive("\n");
+ aprint_normal(": D1 CCU\n");
+
+ sunxi_ccu_print(sc);
+}
Index: src/sys/arch/riscv/sunxi/sun20i_d1_ccu.h
diff -u /dev/null src/sys/arch/riscv/sunxi/sun20i_d1_ccu.h:1.1
--- /dev/null Tue Aug 13 07:20:23 2024
+++ src/sys/arch/riscv/sunxi/sun20i_d1_ccu.h Tue Aug 13 07:20:23 2024
@@ -0,0 +1,249 @@
+/* $NetBSD: sun20i_d1_ccu.h,v 1.1 2024/08/13 07:20:23 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2024 Rui-Xiang Guo
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __CCU_D1_H__
+#define __CCU_D1_H__
+
+#define D1_CLK_PLL_CPU 0
+#define D1_CLK_PLL_DDR 1
+#define D1_CLK_PLL_PERIPH_4X 2
+#define D1_CLK_PLL_PERIPH_2X 3
+#define D1_CLK_PLL_PERIPH_800M 4
+#define D1_CLK_PLL_PERIPH 5
+#define D1_CLK_PLL_PERIPH_DIV3 6
+#define D1_CLK_PLL_VIDEO0_4X 7
+#define D1_CLK_PLL_VIDEO0_2X 8
+#define D1_CLK_PLL_VIDEO0 9
+#define D1_CLK_PLL_VIDEO1_4X 10
+#define D1_CLK_PLL_VIDEO1_2X 11
+#define D1_CLK_PLL_VIDEO1 12
+#define D1_CLK_PLL_VE 13
+#define D1_CLK_PLL_AUDIO0_4X 14
+#define D1_CLK_PLL_AUDIO0_2X 15
+#define D1_CLK_PLL_AUDIO0 16
+#define D1_CLK_PLL_AUDIO1 17
+#define D1_CLK_PLL_AUDIO1_DIV2 18
+#define D1_CLK_PLL_AUDIO1_DIV5 19
+#define D1_CLK_CPU 20
+#define D1_CLK_CPU_AXI 21
+#define D1_CLK_CPU_APB 22
+#define D1_CLK_PSI 23
+#define D1_CLK_APB0 24
+#define D1_CLK_APB1 25
+#define D1_CLK_MBUS 26
+#define D1_CLK_DE 27
+#define D1_CLK_BUS_DE 28
+#define D1_CLK_DI 29
+#define D1_CLK_BUS_DI 30
+#define D1_CLK_G2D 31
+#define D1_CLK_BUS_G2D 32
+#define D1_CLK_CE 33
+#define D1_CLK_BUS_CE 34
+#define D1_CLK_VE 35
+#define D1_CLK_BUS_VE 36
+#define D1_CLK_BUS_DMA 37
+#define D1_CLK_BUS_MSGBOX0 38
+#define D1_CLK_BUS_MSGBOX1 39
+#define D1_CLK_BUS_MSGBOX2 40
+#define D1_CLK_BUS_SPINLOCK 41
+#define D1_CLK_BUS_HSTIMER 42
+#define D1_CLK_AVS 43
+#define D1_CLK_BUS_DBGSYS 44
+#define D1_CLK_BUS_PWM 45
+#define D1_CLK_BUS_IOMMU 46
+#define D1_CLK_DRAM 47
+#define D1_CLK_MBUS_DMA 48
+#define D1_CLK_MBUS_VE 49
+#define D1_CLK_MBUS_CE 50
+#define D1_CLK_MBUS_TVIN 51
+#define D1_CLK_MBUS_CSI 52
+#define D1_CLK_MBUS_G2D 53
+#define D1_CLK_MBUS_RISCV 54
+#define D1_CLK_BUS_DRAM 55
+#define D1_CLK_MMC0 56
+#define D1_CLK_MMC1 57
+#define D1_CLK_MMC2 58
+#define D1_CLK_BUS_MMC0 59
+#define D1_CLK_BUS_MMC1 60
+#define D1_CLK_BUS_MMC2 61
+#define D1_CLK_BUS_UART0 62
+#define D1_CLK_BUS_UART1 63
+#define D1_CLK_BUS_UART2 64
+#define D1_CLK_BUS_UART3 65
+#define D1_CLK_BUS_UART4 66
+#define D1_CLK_BUS_UART5 67
+#define D1_CLK_BUS_I2C0 68
+#define D1_CLK_BUS_I2C1 69
+#define D1_CLK_BUS_I2C2 70
+#define D1_CLK_BUS_I2C3 71
+#define D1_CLK_SPI0 72
+#define D1_CLK_SPI1 73
+#define D1_CLK_BUS_SPI0 74
+#define D1_CLK_BUS_SPI1 75
+#define D1_CLK_EMAC_25M 76
+#define D1_CLK_BUS_EMAC 77
+#define D1_CLK_IRTX 78
+#define D1_CLK_BUS_IRTX 79
+#define D1_CLK_BUS_GPADC 80
+#define D1_CLK_BUS_THS 81
+#define D1_CLK_I2S0 82
+#define D1_CLK_I2S1 83
+#define D1_CLK_I2S2 84
+#define D1_CLK_I2S2_ASRC 85
+#define D1_CLK_BUS_I2S0 86
+#define D1_CLK_BUS_I2S1 87
+#define D1_CLK_BUS_I2S2 88
+#define D1_CLK_SPDIF_TX 89
+#define D1_CLK_SPDIF_RX 90
+#define D1_CLK_BUS_SPDIF 91
+#define D1_CLK_DMIC 92
+#define D1_CLK_BUS_DMIC 93
+#define D1_CLK_AUDIO_DAC 94
+#define D1_CLK_AUDIO_ADC 95
+#define D1_CLK_BUS_AUDIO 96
+#define D1_CLK_USB_PHY0 97
+#define D1_CLK_USB_PHY1 98
+#define D1_CLK_BUS_OHCI0 99
+#define D1_CLK_BUS_OHCI1 100
+#define D1_CLK_BUS_EHCI0 101
+#define D1_CLK_BUS_EHCI1 102
+#define D1_CLK_BUS_OTG 103
+#define D1_CLK_BUS_LRADC 104
+#define D1_CLK_BUS_DPSS_TOP 105
+#define D1_CLK_HDMI_24M 106
+#define D1_CLK_HDMI_CEC_32K 107
+#define D1_CLK_HDMI_CEC 108
+#define D1_CLK_BUS_HDMI 109
+#define D1_CLK_DSI 110
+#define D1_CLK_BUS_DSI 111
+#define D1_CLK_TCONLCD 112
+#define D1_CLK_BUS_TCONLCD 113
+#define D1_CLK_TCONTV 114
+#define D1_CLK_BUS_TCONTV 115
+#define D1_CLK_TVE 116
+#define D1_CLK_BUS_TVE_TOP 117
+#define D1_CLK_BUS_TVE 118
+#define D1_CLK_TVD 119
+#define D1_CLK_BUS_TVD_TOP 120
+#define D1_CLK_BUS_TVD 121
+#define D1_CLK_LEDC 122
+#define D1_CLK_BUS_LEDC 123
+#define D1_CLK_CSI_TOP 124
+#define D1_CLK_CSI_MCLK 125
+#define D1_CLK_BUS_CSI 126
+#define D1_CLK_TPADC 127
+#define D1_CLK_BUS_TPADC 128
+#define D1_CLK_BUS_TZMA 129
+#define D1_CLK_DSP 130
+#define D1_CLK_BUS_DSP_CFG 131
+#define D1_CLK_RISCV 132
+#define D1_CLK_RISCV_AXI 133
+#define D1_CLK_BUS_RISCV_CFG 134
+#define D1_CLK_FANOUT_24M 135
+#define D1_CLK_FANOUT_12M 136
+#define D1_CLK_FANOUT_16M 137
+#define D1_CLK_FANOUT_25M 138
+#define D1_CLK_FANOUT_32K 139
+#define D1_CLK_FANOUT_27M 140
+#define D1_CLK_FANOUT_PCLK 141
+#define D1_CLK_FANOUT0 142
+#define D1_CLK_FANOUT1 143
+#define D1_CLK_FANOUT2 144
+#define D1_CLK_BUS_CAN0 145
+#define D1_CLK_BUS_CAN1 146
+
+#define D1_RST_MBUS 0
+#define D1_RST_BUS_DE 1
+#define D1_RST_BUS_DI 2
+#define D1_RST_BUS_G2D 3
+#define D1_RST_BUS_CE 4
+#define D1_RST_BUS_VE 5
+#define D1_RST_BUS_DMA 6
+#define D1_RST_BUS_MSGBOX0 7
+#define D1_RST_BUS_MSGBOX1 8
+#define D1_RST_BUS_MSGBOX2 9
+#define D1_RST_BUS_SPINLOCK 10
+#define D1_RST_BUS_HSTIMER 11
+#define D1_RST_BUS_DBGSYS 12
+#define D1_RST_BUS_PWM 13
+#define D1_RST_BUS_DRAM 14
+#define D1_RST_BUS_MMC0 15
+#define D1_RST_BUS_MMC1 16
+#define D1_RST_BUS_MMC2 17
+#define D1_RST_BUS_UART0 18
+#define D1_RST_BUS_UART1 19
+#define D1_RST_BUS_UART2 20
+#define D1_RST_BUS_UART3 21
+#define D1_RST_BUS_UART4 22
+#define D1_RST_BUS_UART5 23
+#define D1_RST_BUS_I2C0 24
+#define D1_RST_BUS_I2C1 25
+#define D1_RST_BUS_I2C2 26
+#define D1_RST_BUS_I2C3 27
+#define D1_RST_BUS_SPI0 28
+#define D1_RST_BUS_SPI1 29
+#define D1_RST_BUS_EMAC 30
+#define D1_RST_BUS_IRTX 31
+#define D1_RST_BUS_GPADC 32
+#define D1_RST_BUS_THS 33
+#define D1_RST_BUS_I2S0 34
+#define D1_RST_BUS_I2S1 35
+#define D1_RST_BUS_I2S2 36
+#define D1_RST_BUS_SPDIF 37
+#define D1_RST_BUS_DMIC 38
+#define D1_RST_BUS_AUDIO 39
+#define D1_RST_USB_PHY0 40
+#define D1_RST_USB_PHY1 41
+#define D1_RST_BUS_OHCI0 42
+#define D1_RST_BUS_OHCI1 43
+#define D1_RST_BUS_EHCI0 44
+#define D1_RST_BUS_EHCI1 45
+#define D1_RST_BUS_OTG 46
+#define D1_RST_BUS_LRADC 47
+#define D1_RST_BUS_DPSS_TOP 48
+#define D1_RST_BUS_HDMI_SUB 49
+#define D1_RST_BUS_HDMI_MAIN 50
+#define D1_RST_BUS_DSI 51
+#define D1_RST_BUS_TCONLCD 52
+#define D1_RST_BUS_TCONTV 53
+#define D1_RST_BUS_LVDS 54
+#define D1_RST_BUS_TVE 55
+#define D1_RST_BUS_TVE_TOP 56
+#define D1_RST_BUS_TVD 57
+#define D1_RST_BUS_TVD_TOP 58
+#define D1_RST_BUS_LEDC 59
+#define D1_RST_BUS_CSI 60
+#define D1_RST_BUS_TPADC 61
+#define D1_RST_BUS_DSP 62
+#define D1_RST_BUS_DSP_CFG 63
+#define D1_RST_BUS_DSP_DBG 64
+#define D1_RST_BUS_RISCV_CFG 65
+#define D1_RST_BUS_CAN0 66
+#define D1_RST_BUS_CAN1 67
+
+#endif /* __CCU_D1_H__ */
Index: src/sys/arch/riscv/sunxi/sun20i_d1_gpio.c
diff -u /dev/null src/sys/arch/riscv/sunxi/sun20i_d1_gpio.c:1.1
--- /dev/null Tue Aug 13 07:20:23 2024
+++ src/sys/arch/riscv/sunxi/sun20i_d1_gpio.c Tue Aug 13 07:20:23 2024
@@ -0,0 +1,139 @@
+/* $NetBSD: sun20i_d1_gpio.c,v 1.1 2024/08/13 07:20:23 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2024 Rui-Xiang Guo
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: sun20i_d1_gpio.c,v 1.1 2024/08/13 07:20:23 skrll Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/types.h>
+
+#include <arm/sunxi/sunxi_gpio.h>
+
+static const struct sunxi_gpio_pins d1_pins[] = {
+ {"PB0", 1, 0, {"gpio_in", "gpio_out", "pwm3", "ir", "i2c2", "spi1", "uart0", "uart2", "spdif", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0},
+ {"PB1", 1, 1, {"gpio_in", "gpio_out", "pwm4", "i2s2", "i2c2", "i2s2", "uart0", "uart2", "ir", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1},
+ {"PB2", 1, 2, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c0", "i2s2", "lcd0", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2},
+ {"PB3", 1, 3, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c0", "i2s2", "lcd0", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3},
+ {"PB4", 1, 4, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c1", "i2s2", "lcd0", "uart5", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4},
+ {"PB5", 1, 5, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c1", "pwm0", "lcd0", "uart5", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5},
+ {"PB6", 1, 6, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c3", "pwm1", "lcd0", "uart3", "cpu", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6},
+ {"PB7", 1, 7, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c3", "ir", "lcd0", "uart3", "cpu", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7},
+ {"PB8", 1, 8, {"gpio_in", "gpio_out", "dmic", "pwm5", "i2c2", "spi1", "uart0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 8},
+ {"PB9", 1, 9, {"gpio_in", "gpio_out", "dmic", "pwm6", "i2c2", "spi1", "uart0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 9},
+ {"PB10", 1, 10, {"gpio_in", "gpio_out", "dmic", "pwm7", "i2c0", "spi1", "clk", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 10},
+ {"PB11", 1, 11, {"gpio_in", "gpio_out", "dmic", "pwm2", "i2c0", "spi1", "clk", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 11},
+ {"PB12", 1, 12, {"gpio_in", "gpio_out", "dmic", "pwm0", "spdif", "spi1", "clk", "ir", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 12},
+
+ {"PC0", 2, 0, {"gpio_in", "gpio_out", "uart2", "i2c2", "ledc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0},
+ {"PC1", 2, 1, {"gpio_in", "gpio_out", "uart2", "i2c2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1},
+ {"PC2", 2, 2, {"gpio_in", "gpio_out", "spi0", "mmc2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2},
+ {"PC3", 2, 3, {"gpio_in", "gpio_out", "spi0", "mmc2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3},
+ {"PC4", 2, 4, {"gpio_in", "gpio_out", "spi0", "mmc2", "boot", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4},
+ {"PC5", 2, 5, {"gpio_in", "gpio_out", "spi0", "mmc2", "boot", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5},
+ {"PC6", 2, 6, {"gpio_in", "gpio_out", "spi0", "mmc2", "uart3", "i2c3", "dbg", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6},
+ {"PC7", 2, 7, {"gpio_in", "gpio_out", "spi0", "mmc2", "uart3", "i2c3", "tcon", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7},
+
+ {"PD0", 3, 0, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "i2c0", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0},
+ {"PD1", 3, 1, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1},
+ {"PD2", 3, 2, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2},
+ {"PD3", 3, 3, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3},
+ {"PD4", 3, 4, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4},
+ {"PD5", 3, 5, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5},
+ {"PD6", 3, 6, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6},
+ {"PD7", 3, 7, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7},
+ {"PD8", 3, 8, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 8},
+ {"PD9", 3, 9, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "pwm6", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 9},
+ {"PD10", 3, 10, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 10},
+ {"PD11", 3, 11, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 11},
+ {"PD12", 3, 12, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "i2c0", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 12},
+ {"PD13", 3, 13, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 13},
+ {"PD14", 3, 14, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 14},
+ {"PD15", 3, 15, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "ir", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 15},
+ {"PD16", 3, 16, {"gpio_in", "gpio_out", "lcd0", "lvds1", "dmic", "pwm0", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 16},
+ {"PD17", 3, 17, {"gpio_in", "gpio_out", "lcd0", "lvds1", "dmic", "pwm1", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 17},
+ {"PD18", 3, 18, {"gpio_in", "gpio_out", "lcd0", "lvds1", "dmic", "pwm2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 18},
+ {"PD19", 3, 19, {"gpio_in", "gpio_out", "lcd0", "lvds1", "dmic", "pwm3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 19},
+ {"PD20", 3, 20, {"gpio_in", "gpio_out", "lcd0", "i2c2", "dmic", "pwm4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 20},
+ {"PD21", 3, 21, {"gpio_in", "gpio_out", "lcd0", "i2c2", "uart1", "pwm5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 21},
+ {"PD22", 3, 22, {"gpio_in", "gpio_out", "spdif", "ir", "uart1", "pwm7", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 22},
+
+ {"PE0", 4, 0, {"gpio_in", "gpio_out", "ncsi0", "uart2", "i2c1", "lcd0", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0},
+ {"PE1", 4, 1, {"gpio_in", "gpio_out", "ncsi0", "uart2", "i2c1", "lcd0", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1},
+ {"PE2", 4, 2, {"gpio_in", "gpio_out", "ncsi0", "uart2", "i2c0", "clk", "uart0", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2},
+ {"PE3", 4, 3, {"gpio_in", "gpio_out", "ncsi0", "uart2", "i2c0", "clk", "uart0", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3},
+ {"PE4", 4, 4, {"gpio_in", "gpio_out", "ncsi0", "uart4", "i2c2", "clk", "jtag", "jtag", "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4},
+ {"PE5", 4, 5, {"gpio_in", "gpio_out", "ncsi0", "uart4", "i2c2", "ledc", "jtag", "jtag", "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5},
+ {"PE6", 4, 6, {"gpio_in", "gpio_out", "ncsi0", "uart5", "i2c3", "spdif", "jtag", "jtag", "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6},
+ {"PE7", 4, 7, {"gpio_in", "gpio_out", "ncsi0", "uart5", "i2c3", "spdif", "jtag", "jtag", "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7},
+ {"PE8", 4, 8, {"gpio_in", "gpio_out", "ncsi0", "uart1", "pwm2", "uart3", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 8},
+ {"PE9", 4, 9, {"gpio_in", "gpio_out", "ncsi0", "uart1", "pwm3", "uart3", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 9},
+ {"PE10", 4, 10, {"gpio_in", "gpio_out", "ncsi0", "uart1", "pwm4", "ir", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 10},
+ {"PE11", 4, 11, {"gpio_in", "gpio_out", "ncsi0", "uart1", "i2s0", "i2s0", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 11},
+ {"PE12", 4, 12, {"gpio_in", "gpio_out", "i2c2", "ncsi0", "i2s0", "i2s0", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 12},
+ {"PE13", 4, 13, {"gpio_in", "gpio_out", "i2c2", "pwm5", "i2s0", "i2s0", "dmic", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 13},
+ {"PE14", 4, 14, {"gpio_in", "gpio_out", "i2c1", "jtag", "i2s0", "i2s0", "dmic", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 14},
+ {"PE15", 4, 15, {"gpio_in", "gpio_out", "i2c1", "jtag", "pwm6", "i2s0", "dmic", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 15},
+ {"PE16", 4, 16, {"gpio_in", "gpio_out", "i2c3", "jtag", "pwm7", "i2s0", "dmic", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 16},
+ {"PE17", 4, 17, {"gpio_in", "gpio_out", "i2c3", "jtag", "ir", "i2s0", "dmic", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 17},
+
+ {"PF0", 5, 0, {"gpio_in", "gpio_out", "mmc0", NULL, "jtag", "i2s2", "i2s2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0},
+ {"PF1", 5, 1, {"gpio_in", "gpio_out", "mmc0", NULL, "jtag", "i2s2", "i2s2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1},
+ {"PF2", 5, 2, {"gpio_in", "gpio_out", "mmc0", "uart0", "i2c0", "ledc", "spdif", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2},
+ {"PF3", 5, 3, {"gpio_in", "gpio_out", "mmc0", NULL, "jtag", "i2s2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3},
+ {"PF4", 5, 4, {"gpio_in", "gpio_out", "mmc0", "uart0", "i2c0", "pwm6", "ir", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4},
+ {"PF5", 5, 5, {"gpio_in", "gpio_out", "mmc0", NULL, "jtag", "i2s2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5},
+ {"PF6", 5, 6, {"gpio_in", "gpio_out", NULL, "spdif", "ir", "i2s2", "pwm5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6},
+
+ {"PG0", 6, 0, {"gpio_in", "gpio_out", "mmc1", "uart3", "emac", "pwm7", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0},
+ {"PG1", 6, 1, {"gpio_in", "gpio_out", "mmc1", "uart3", "emac", "pwm6", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1},
+ {"PG2", 6, 2, {"gpio_in", "gpio_out", "mmc1", "uart3", "emac", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2},
+ {"PG3", 6, 3, {"gpio_in", "gpio_out", "mmc1", "uart3", "emac", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3},
+ {"PG4", 6, 4, {"gpio_in", "gpio_out", "mmc1", "uart5", "emac", "pwm5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4},
+ {"PG5", 6, 5, {"gpio_in", "gpio_out", "mmc1", "uart5", "emac", "pwm4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5},
+ {"PG6", 6, 6, {"gpio_in", "gpio_out", "uart1", "i2c2", "emac", "pwm1", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6},
+ {"PG7", 6, 7, {"gpio_in", "gpio_out", "uart1", "i2c2", "emac", "spdif", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7},
+ {"PG8", 6, 8, {"gpio_in", "gpio_out", "uart1", "i2c1", "emac", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 8},
+ {"PG9", 6, 9, {"gpio_in", "gpio_out", "uart1", "i2c1", "emac", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 9},
+ {"PG10", 6, 10, {"gpio_in", "gpio_out", "pwm3", "i2c3", "emac", "clk", "ir", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 10},
+ {"PG11", 6, 11, {"gpio_in", "gpio_out", "i2s1", "i2c3", "emac", "clk", "tcon", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 11},
+ {"PG12", 6, 12, {"gpio_in", "gpio_out", "i2s1", "i2c0", "emac", "clk", "pwm0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 12},
+ {"PG13", 6, 13, {"gpio_in", "gpio_out", "i2s1", "i2c0", "emac", "pwm2", "ledc", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 13},
+ {"PG14", 6, 14, {"gpio_in", "gpio_out", "i2s1", "i2c2", "emac", "i2s1", "spi0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 14},
+ {"PG15", 6, 15, {"gpio_in", "gpio_out", "i2s1", "i2c2", "emac", "i2s1", "spi0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 15},
+ {"PG16", 6, 16, {"gpio_in", "gpio_out", "ir", "tcon", "pwm5", "clk", "spdif", "ledc", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 16},
+ {"PG17", 6, 17, {"gpio_in", "gpio_out", "uart2", "i2c3", "pwm7", "clk", "ir", "uart0", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 17},
+ {"PG18", 6, 18, {"gpio_in", "gpio_out", "uart2", "i2c3", "pwm6", "clk", "spdif", "uart0", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 18},
+};
+
+const struct sunxi_gpio_padconf sun20i_d1_padconf = {
+ .npins = __arraycount(d1_pins),
+ .pins = d1_pins,
+};
