Module Name: src
Committed By: rillig
Date: Sun Mar 10 17:34:47 UTC 2024
Modified Files:
src/sys/arch/sparc/include: ctlreg.h
src/sys/arch/sparc64/include: ctlreg.h
Log Message:
sparc: fix snprintb formats for SFSR_BITS
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/sparc/include/ctlreg.h
cvs rdiff -u -r1.70 -r1.71 src/sys/arch/sparc64/include/ctlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc/include/ctlreg.h
diff -u src/sys/arch/sparc/include/ctlreg.h:1.31 src/sys/arch/sparc/include/ctlreg.h:1.32
--- src/sys/arch/sparc/include/ctlreg.h:1.31 Mon Sep 6 21:56:03 2021
+++ src/sys/arch/sparc/include/ctlreg.h Sun Mar 10 17:34:46 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.31 2021/09/06 21:56:03 andvar Exp $ */
+/* $NetBSD: ctlreg.h,v 1.32 2024/03/10 17:34:46 rillig Exp $ */
/*
* Copyright (c) 1996
@@ -376,7 +376,7 @@
#define SFSR_BITS "\177\020" \
"b\21EM\0b\20CS\0b\17SB\0f\15\2PERR\0" \
"b\14UC\0b\13TO\0b\12BE\0f\10\2LVL\0" \
- "f\05\3AT\0f\02\3FT\0b\01FAV\0b\01OW\0"
+ "f\05\3AT\0f\02\3FT\0b\01FAV\0b\00OW\0"
/* [4m] Synchronous Fault Types */
#define SFSR_FT_NONE (0 << 2) /* no fault */
Index: src/sys/arch/sparc64/include/ctlreg.h
diff -u src/sys/arch/sparc64/include/ctlreg.h:1.70 src/sys/arch/sparc64/include/ctlreg.h:1.71
--- src/sys/arch/sparc64/include/ctlreg.h:1.70 Fri Feb 2 22:33:42 2024
+++ src/sys/arch/sparc64/include/ctlreg.h Sun Mar 10 17:34:47 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.70 2024/02/02 22:33:42 andvar Exp $ */
+/* $NetBSD: ctlreg.h,v 1.71 2024/03/10 17:34:47 rillig Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -306,9 +306,10 @@
SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV)
#define SFSR_BITS "\177\20" \
- "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" \
- "b\11NF\0" "b\10PRIV\0" "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" \
- "b\3W\0" "b\2OW\0" "b\1FV\0"
+ "f\20\30ASI\0" "b\15VAT\0" "b\14VAD\0" \
+ "b\13NFO\0" "b\12ASI\0" "b\11A\0" "b\10NF\0" \
+ "b\07PRIV\0" "b\06E\0" "b\05NUCLEUS\0" "b\04SECONDCTX\0" \
+ "b\03PRIV\0" "b\02W\0" "b\01OW\0" "b\00FV\0"
/* ASFR bits */
#define ASFR_ME 0x100000000LL
