Module Name: src
Committed By: msaitoh
Date: Thu Oct 26 18:02:51 UTC 2023
Modified Files:
src/sys/dev/ic: dwc_eqos.c dwc_eqos_reg.h dwc_eqos_var.h
src/sys/dev/pci: if_eqos_pci.c
Log Message:
eqos(4): Set TX/RX DMA burst length to improve performance.
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/dev/ic/dwc_eqos.c
cvs rdiff -u -r1.7 -r1.8 src/sys/dev/ic/dwc_eqos_reg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/dev/ic/dwc_eqos_var.h
cvs rdiff -u -r1.1 -r1.2 src/sys/dev/pci/if_eqos_pci.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/dwc_eqos.c
diff -u src/sys/dev/ic/dwc_eqos.c:1.26 src/sys/dev/ic/dwc_eqos.c:1.27
--- src/sys/dev/ic/dwc_eqos.c:1.26 Thu Oct 26 13:00:13 2023
+++ src/sys/dev/ic/dwc_eqos.c Thu Oct 26 18:02:50 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos.c,v 1.26 2023/10/26 13:00:13 msaitoh Exp $ */
+/* $NetBSD: dwc_eqos.c,v 1.27 2023/10/26 18:02:50 msaitoh Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill <jmcne...@invisible.ca>
@@ -38,7 +38,7 @@
#include "opt_net_mpsafe.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.26 2023/10/26 13:00:13 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.27 2023/10/26 18:02:50 msaitoh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -612,12 +612,16 @@ eqos_init_locked(struct eqos_softc *sc)
val |= GMAC_DMA_CHAN0_CONTROL_PBLX8;
WR4(sc, GMAC_DMA_CHAN0_CONTROL, val);
val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL);
+ val &= ~GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_MASK;
+ val |= (sc->sc_dma_txpbl << GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_SHIFT);
val |= GMAC_DMA_CHAN0_TX_CONTROL_OSP;
val |= GMAC_DMA_CHAN0_TX_CONTROL_START;
WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);
val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL);
- val &= ~GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK;
+ val &= ~(GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK |
+ GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_MASK);
val |= (MCLBYTES << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT);
+ val |= (sc->sc_dma_rxpbl << GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_SHIFT);
val |= GMAC_DMA_CHAN0_RX_CONTROL_START;
WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);
@@ -1259,6 +1263,24 @@ eqos_get_eaddr(struct eqos_softc *sc, ui
}
static void
+eqos_get_dma_pbl(struct eqos_softc *sc)
+{
+ prop_dictionary_t prop = device_properties(sc->sc_dev);
+ uint32_t pbl;
+
+ /* Set default values. */
+ sc->sc_dma_txpbl = sc->sc_dma_rxpbl = EQOS_DMA_PBL_DEFAULT;
+
+ /* Get values from props. */
+ if (prop_dictionary_get_uint32(prop, "snps,pbl", &pbl) && pbl)
+ sc->sc_dma_txpbl = sc->sc_dma_rxpbl = pbl;
+ if (prop_dictionary_get_uint32(prop, "snps,txpbl", &pbl) && pbl)
+ sc->sc_dma_txpbl = pbl;
+ if (prop_dictionary_get_uint32(prop, "snps,rxpbl", &pbl) && pbl)
+ sc->sc_dma_rxpbl = pbl;
+}
+
+static void
eqos_axi_configure(struct eqos_softc *sc)
{
prop_dictionary_t prop = device_properties(sc->sc_dev);
@@ -1493,6 +1515,9 @@ eqos_attach(struct eqos_softc *sc)
return error;
}
+ /* Get DMA burst length */
+ eqos_get_dma_pbl(sc);
+
/* Configure AXI Bus mode parameters */
eqos_axi_configure(sc);
Index: src/sys/dev/ic/dwc_eqos_reg.h
diff -u src/sys/dev/ic/dwc_eqos_reg.h:1.7 src/sys/dev/ic/dwc_eqos_reg.h:1.8
--- src/sys/dev/ic/dwc_eqos_reg.h:1.7 Tue Oct 17 10:23:00 2023
+++ src/sys/dev/ic/dwc_eqos_reg.h Thu Oct 26 18:02:50 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos_reg.h,v 1.7 2023/10/17 10:23:00 msaitoh Exp $ */
+/* $NetBSD: dwc_eqos_reg.h,v 1.8 2023/10/26 18:02:50 msaitoh Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill <jmcne...@invisible.ca>
@@ -250,9 +250,13 @@
#define GMAC_DMA_CHAN0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT)
#define GMAC_DMA_CHAN0_CONTROL_PBLX8 (1U << 16)
#define GMAC_DMA_CHAN0_TX_CONTROL 0x1104
+#define GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_SHIFT 16
+#define GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_MASK (0x3FU << GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_SHIFT)
#define GMAC_DMA_CHAN0_TX_CONTROL_OSP (1U << 4)
#define GMAC_DMA_CHAN0_TX_CONTROL_START (1U << 0)
#define GMAC_DMA_CHAN0_RX_CONTROL 0x1108
+#define GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_SHIFT 16
+#define GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_MASK (0x3FU << GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_SHIFT)
#define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT 1
#define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK (0x3FFFU << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT)
#define GMAC_DMA_CHAN0_RX_CONTROL_START (1U << 0)
Index: src/sys/dev/ic/dwc_eqos_var.h
diff -u src/sys/dev/ic/dwc_eqos_var.h:1.5 src/sys/dev/ic/dwc_eqos_var.h:1.6
--- src/sys/dev/ic/dwc_eqos_var.h:1.5 Mon Oct 23 15:29:38 2023
+++ src/sys/dev/ic/dwc_eqos_var.h Thu Oct 26 18:02:50 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos_var.h,v 1.5 2023/10/23 15:29:38 msaitoh Exp $ */
+/* $NetBSD: dwc_eqos_var.h,v 1.6 2023/10/26 18:02:50 msaitoh Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill <jmcne...@invisible.ca>
@@ -36,6 +36,7 @@
#include <dev/ic/dwc_eqos_reg.h>
#define EQOS_DMA_DESC_COUNT 256
+#define EQOS_DMA_PBL_DEFAULT 8
struct eqos_bufmap {
bus_dmamap_t map;
@@ -60,8 +61,9 @@ struct eqos_softc {
int sc_phy_id;
uint32_t sc_csr_clock;
uint32_t sc_clock_range;
-
uint32_t sc_hw_feature[4];
+ uint32_t sc_dma_txpbl;
+ uint32_t sc_dma_rxpbl;
struct ethercom sc_ec;
struct mii_data sc_mii;
Index: src/sys/dev/pci/if_eqos_pci.c
diff -u src/sys/dev/pci/if_eqos_pci.c:1.1 src/sys/dev/pci/if_eqos_pci.c:1.2
--- src/sys/dev/pci/if_eqos_pci.c:1.1 Fri Oct 20 10:09:43 2023
+++ src/sys/dev/pci/if_eqos_pci.c Thu Oct 26 18:02:51 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: if_eqos_pci.c,v 1.1 2023/10/20 10:09:43 msaitoh Exp $ */
+/* $NetBSD: if_eqos_pci.c,v 1.2 2023/10/26 18:02:51 msaitoh Exp $ */
/*-
* Copyright (c) 2023 Masanobu SAITOH <msai...@netbsd.org>
@@ -35,7 +35,7 @@
#include "opt_net_mpsafe.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_eqos_pci.c,v 1.1 2023/10/20 10:09:43 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_eqos_pci.c,v 1.2 2023/10/26 18:02:51 msaitoh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -105,6 +105,7 @@ eqos_pci_attach(device_t parent, device_
struct pci_attach_args *pa =aux;
const pci_chipset_tag_t pc = pa->pa_pc;
const pcitag_t tag = pa->pa_tag;
+ prop_dictionary_t prop;
bus_space_tag_t memt;
bus_space_handle_t memh;
int counts[PCI_INTR_TYPE_SIZE];
@@ -112,6 +113,7 @@ eqos_pci_attach(device_t parent, device_
bus_size_t memsize;
pcireg_t memtype;
const char *intrstr;
+ uint32_t dma_pbl = 0;
psc->sc_pc = pc;
psc->sc_tag = tag;
@@ -126,6 +128,7 @@ eqos_pci_attach(device_t parent, device_
sc->sc_dev = self;
sc->sc_bst = memt;
sc->sc_bsh = memh;
+ prop = device_properties(sc->sc_dev);
#if 0 /* I don't know why dmat64 doesn't work... */
if (pci_dma64_available(pa)) {
@@ -142,6 +145,7 @@ eqos_pci_attach(device_t parent, device_
switch (psc->sc_pcidevid) {
case PCI_PRODUCT_INTEL_EHL_ETH:
sc->sc_csr_clock = 204800000;
+ dma_pbl = 32;
break;
case PCI_PRODUCT_INTEL_EHL_PSE_ETH_0_RGMII:
case PCI_PRODUCT_INTEL_EHL_PSE_ETH_1_RGMII:
@@ -150,10 +154,21 @@ eqos_pci_attach(device_t parent, device_
case PCI_PRODUCT_INTEL_EHL_PSE_ETH_0_SGMII_2_5G:
case PCI_PRODUCT_INTEL_EHL_PSE_ETH_1_SGMII_2_5G:
sc->sc_csr_clock = 200000000;
+ dma_pbl = 32;
break;
+#if 0
+ case PCI_PRODUCT_INTEL_QUARTK_ETH:
+ dma_pbl = 16;
+#endif
default:
sc->sc_csr_clock = 200000000; /* XXX */
}
+ /* Defaults */
+ if (dma_pbl != 0) {
+ prop = device_properties(sc->sc_dev);
+ prop_dictionary_set_uint32(prop, "snps,pbl", dma_pbl);
+ }
+
if (eqos_attach(sc) != 0) {
aprint_error_dev(sc->sc_dev, "failed in eqos_attach()\n");
return;
