Module Name: src
Committed By: rin
Date: Fri Jul 7 07:19:36 UTC 2023
Modified Files:
src/sys/dev/pci: virtio_pci.c
src/sys/dev/virtio: virtio_mmio.c
Log Message:
virtio(4): Fix byte order of DMA data for armeb in the same manner as
aarch64eb.
Fix comments to explain what is going on for {arm,aarch64}eb on QEMU.
This is not due to QEMU bugs; it correctly configures everything for
little-endian environment, and we forcibly change byte order only for
CPU cores during kernel bootstrap.
To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/sys/dev/pci/virtio_pci.c
cvs rdiff -u -r1.10 -r1.11 src/sys/dev/virtio/virtio_mmio.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/virtio_pci.c
diff -u src/sys/dev/pci/virtio_pci.c:1.42 src/sys/dev/pci/virtio_pci.c:1.43
--- src/sys/dev/pci/virtio_pci.c:1.42 Wed Apr 19 00:23:45 2023
+++ src/sys/dev/pci/virtio_pci.c Fri Jul 7 07:19:36 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: virtio_pci.c,v 1.42 2023/04/19 00:23:45 yamaguchi Exp $ */
+/* $NetBSD: virtio_pci.c,v 1.43 2023/07/07 07:19:36 rin Exp $ */
/*
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: virtio_pci.c,v 1.42 2023/04/19 00:23:45 yamaguchi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: virtio_pci.c,v 1.43 2023/07/07 07:19:36 rin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -138,15 +138,16 @@ static bool virtio_pci_msix_enabled(stru
#define VIRTIO_MSIX_QUEUE_VECTOR_INDEX 1
/*
- * When using PCI attached virtio on aarch64-eb under Qemu, the IO space
- * suddenly read BIG_ENDIAN where it should stay LITTLE_ENDIAN. The data read
- * 1 byte at a time seem OK but reading bigger lengths result in swapped
- * endian. This is most notable on reading 8 byters since we can't use
- * bus_space_{read,write}_8().
+ * For big-endian aarch64/armv7 on QEMU (and most real HW), only CPU cores
+ * are running in big-endian mode, with all peripheral being configured to
+ * little-endian mode. Their default bus_space(9) functions forcibly swap
+ * byte-order. This guarantees that PIO'ed data from pci(4), e.g., are
+ * correctly handled by bus_space(9), while DMA'ed ones should be swapped
+ * by hand, in violation of virtio(4) specifications.
*/
-#if defined(__aarch64__) && BYTE_ORDER == BIG_ENDIAN
-# define READ_ENDIAN_09 BIG_ENDIAN /* should be LITTLE_ENDIAN */
+#if (defined(__aarch64__) || defined(__arm__)) && BYTE_ORDER == BIG_ENDIAN
+# define READ_ENDIAN_09 BIG_ENDIAN
# define READ_ENDIAN_10 BIG_ENDIAN
# define STRUCT_ENDIAN_09 BIG_ENDIAN
# define STRUCT_ENDIAN_10 LITTLE_ENDIAN
Index: src/sys/dev/virtio/virtio_mmio.c
diff -u src/sys/dev/virtio/virtio_mmio.c:1.10 src/sys/dev/virtio/virtio_mmio.c:1.11
--- src/sys/dev/virtio/virtio_mmio.c:1.10 Wed Apr 19 00:23:45 2023
+++ src/sys/dev/virtio/virtio_mmio.c Fri Jul 7 07:19:36 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: virtio_mmio.c,v 1.10 2023/04/19 00:23:45 yamaguchi Exp $ */
+/* $NetBSD: virtio_mmio.c,v 1.11 2023/07/07 07:19:36 rin Exp $ */
/* $OpenBSD: virtio_mmio.c,v 1.2 2017/02/24 17:12:31 patrick Exp $ */
/*
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: virtio_mmio.c,v 1.10 2023/04/19 00:23:45 yamaguchi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: virtio_mmio.c,v 1.11 2023/07/07 07:19:36 rin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -68,12 +68,10 @@ __KERNEL_RCSID(0, "$NetBSD: virtio_mmio.
/*
* MMIO configuration space for virtio-mmio v1 is in guest byte order.
*
- * XXX Note that aarch64eb pretends to be little endian. the MMIO registers
- * are in little endian but the device config registers and data structures
- * are in big endian; this is due to a bug in current Qemu.
+ * XXX For big-endian aarch64 and arm, see note in virtio_pci.c.
*/
-#if defined(__aarch64__) && BYTE_ORDER == BIG_ENDIAN
+#if (defined(__aarch64__) || defined(__arm__)) && BYTE_ORDER == BIG_ENDIAN
# define READ_ENDIAN LITTLE_ENDIAN
# define STRUCT_ENDIAN BIG_ENDIAN
#elif BYTE_ORDER == BIG_ENDIAN
