Module Name: src
Committed By: martin
Date: Wed Jul 5 16:09:50 UTC 2023
Modified Files:
src/sys/arch/sparc/dev [netbsd-10]: cgfourteen.c sx.c sxvar.h
src/sys/dev/sbus [netbsd-10]: mgx.c
src/sys/dev/wscons [netbsd-10]: wsdisplay_glyphcache.c
wsdisplay_glyphcachevar.h wsdisplay_vcons.c wsdisplay_vconsvar.h
Log Message:
Pull up following revision(s) (requested by abs in ticket #224):
sys/dev/wscons/wsdisplay_vconsvar.h: revision 1.34
sys/dev/wscons/wsdisplay_glyphcachevar.h: revision 1.6
sys/arch/sparc/dev/cgfourteen.c: revision 1.94
sys/arch/sparc/dev/cgfourteen.c: revision 1.95
sys/dev/sbus/mgx.c: revision 1.21
sys/dev/sbus/mgx.c: revision 1.22
sys/dev/sbus/mgx.c: revision 1.23
sys/dev/wscons/wsdisplay_vcons.c: revision 1.65
sys/dev/wscons/wsdisplay_vcons.c: revision 1.66
sys/dev/wscons/wsdisplay_glyphcache.c: revision 1.12
sys/arch/sparc/dev/sxvar.h: revision 1.5
sys/arch/sparc/dev/sx.c: revision 1.6
sys/arch/sparc/dev/sx.c: revision 1.7
make vcons_putchar_buffer() return a flag indicating if anything actually
changed, skip the actual drawing op if nothing did
add flags for drivers to requesr R2L bit/byte-ordered fonts, default to
L2R, chack them in vcons_load_font() instead of just trusting that we'd get
what we need
initialize the diagnostic register with the value suggested by the SunOS
header. This sets a bunch of undocumented bits and yields a 10% speed increase
when rendering antialiased text.
use macros compatible with xf86-video-suncg14 to issue SX instructions
much more readable, alignment weirdness is handled automatically and code is
interchangable
allow drivers to specify horizontal alignment of glyph cache cells
for things like SX which have alignment restrictions
add counter to periodically drain the instruction queue in order to avoid
stalling the MBus during long SX operations
adapted from xf86-video-suncg14
- use sx_wait() to avoid stalling the MBus
- request 32bit alignment for glyphcache cells
wait for the engine to go idle before issuing rectfill commands
we get occasional overlap with blit commands if we just wait for fifo slots
needs further investigation, it is possible that not all writes to drawing
engine registers are pipelined and of course we don't have docs
following a hunch...
- cache DEC and FG registers, only write them if the value actually changes
- wait for the engine to go idle before writing DEC
- wait for FIFO slots on everything else
with this we avoid waiting if possible and still avoid overlapping blit and
fill commands
To generate a diff of this commit:
cvs rdiff -u -r1.93 -r1.93.4.1 src/sys/arch/sparc/dev/cgfourteen.c
cvs rdiff -u -r1.5 -r1.5.4.1 src/sys/arch/sparc/dev/sx.c
cvs rdiff -u -r1.4 -r1.4.30.1 src/sys/arch/sparc/dev/sxvar.h
cvs rdiff -u -r1.20 -r1.20.4.1 src/sys/dev/sbus/mgx.c
cvs rdiff -u -r1.11 -r1.11.30.1 src/sys/dev/wscons/wsdisplay_glyphcache.c
cvs rdiff -u -r1.5 -r1.5.42.1 src/sys/dev/wscons/wsdisplay_glyphcachevar.h
cvs rdiff -u -r1.64 -r1.64.4.1 src/sys/dev/wscons/wsdisplay_vcons.c
cvs rdiff -u -r1.33 -r1.33.4.1 src/sys/dev/wscons/wsdisplay_vconsvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
