Module Name:    src
Committed By:   andvar
Date:           Sat Mar 25 21:47:10 UTC 2023

Modified Files:
        src/sys/arch/atari/include: video.h
        src/sys/arch/x86/include: specialreg.h

Log Message:
s/Predective/Predictive/ and s/dedected/detected/ in comments.


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/atari/include/video.h
cvs rdiff -u -r1.203 -r1.204 src/sys/arch/x86/include/specialreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/atari/include/video.h
diff -u src/sys/arch/atari/include/video.h:1.8 src/sys/arch/atari/include/video.h:1.9
--- src/sys/arch/atari/include/video.h:1.8	Sun Jul  3 11:30:48 2022
+++ src/sys/arch/atari/include/video.h	Sat Mar 25 21:47:10 2023
@@ -1,4 +1,4 @@
-/*	$NetBSD: video.h,v 1.8 2022/07/03 11:30:48 andvar Exp $	*/
+/*	$NetBSD: video.h,v 1.9 2023/03/25 21:47:10 andvar Exp $	*/
 
 /*
  * Copyright (c) 1995 Leo Weppelman.
@@ -117,7 +117,7 @@ struct video {
 #define	TT_SHOLD	0x1000	/* Sample/hold mode			*/
 
 /* The falcon video modes */
-#define RES_FALAUTO	0	/* Falcon resolution dedected at boot	*/
+#define RES_FALAUTO	0	/* Falcon resolution detected at boot	*/
 #define RES_VGA2	1	/* 640x480,   2 colors			*/
 #define RES_VGA4	2	/* 640x480,   4 colors			*/
 #define RES_VGA16	3	/* 640x480,  16 colors			*/

Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.203 src/sys/arch/x86/include/specialreg.h:1.204
--- src/sys/arch/x86/include/specialreg.h:1.203	Fri Feb 17 09:53:24 2023
+++ src/sys/arch/x86/include/specialreg.h	Sat Mar 25 21:47:10 2023
@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.203 2023/02/17 09:53:24 msaitoh Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.204 2023/03/25 21:47:10 andvar Exp $	*/
 
 /*
  * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -1065,7 +1065,7 @@
 #define CPUID_AMDEXT2_FSRC	  __BIT(11) /* Fast Short Rep Cmpsb */
 #define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
 #define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
-#define CPUID_AMDEXT2_EPSF	  __BIT(18) /* Enhanced Predective Store Fwd */
+#define CPUID_AMDEXT2_EPSF	  __BIT(18) /* Enhanced Predictive Store Fwd */
 
 #define CPUID_AMDEXT2_FLAGS	 "\20"					      \
 	"\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing"		      \

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