Module Name:    src
Committed By:   riastradh
Date:           Wed Mar  1 08:18:04 UTC 2023

Modified Files:
        src/sys/arch/mips/mips: locore.S

Log Message:
mips: Optimization: Omit needless membar when triggering softint.

When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10


To generate a diff of this commit:
cvs rdiff -u -r1.229 -r1.230 src/sys/arch/mips/mips/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.229 src/sys/arch/mips/mips/locore.S:1.230
--- src/sys/arch/mips/mips/locore.S:1.229	Thu Feb 23 14:56:00 2023
+++ src/sys/arch/mips/mips/locore.S	Wed Mar  1 08:18:03 2023
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.229 2023/02/23 14:56:00 riastradh Exp $	*/
+/*	$NetBSD: locore.S,v 1.230 2023/03/01 08:18:03 riastradh Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -63,7 +63,7 @@
 #include <mips/trap.h>
 #include <mips/locore.h>
 
-RCSID("$NetBSD: locore.S,v 1.229 2023/02/23 14:56:00 riastradh Exp $")
+RCSID("$NetBSD: locore.S,v 1.230 2023/03/01 08:18:03 riastradh Exp $")
 
 #include "assym.h"
 
@@ -429,7 +429,13 @@ NESTED(softint_fast_dispatch, CALLFRAME_
 	nop					# patchable load delay slot
 	SYNC_PRODUCER /* XXX fixup */	/* for mutex_enter; see cpu_switchto */
 	PTR_S	MIPS_CURLWP, CPU_INFO_CURLWP(s1)	#    ...
-	SYNC_DEKKER /* XXX fixup */	/* for mutex_enter; see cpu_switchto */
+	/*
+	 * No need for barrier after ci->ci_curlwp = softlwp -- when we
+	 * enter a softint lwp, it can't be holding any mutexes, so it
+	 * can't release any until after it has acquired them, so we
+	 * need not participate in the protocol with mutex_vector_enter
+	 * barriers here.
+	 */
 	move	s2, sp					# remember sp
 	move	s3, t0					# remember curpcb
 

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