Module Name: src
Committed By: ryo
Date: Thu Dec 22 06:58:08 UTC 2022
Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c
src/sys/arch/arm/arm: cpufunc.c
src/sys/arch/arm/arm32: arm32_boot.c
Log Message:
Explicitly disable overflow interrupts before enabling the cycle counter.
To generate a diff of this commit:
cvs rdiff -u -r1.70 -r1.71 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.184 -r1.185 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/arm32/arm32_boot.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.70 src/sys/arch/aarch64/aarch64/cpu.c:1.71
--- src/sys/arch/aarch64/aarch64/cpu.c:1.70 Sun May 29 16:14:41 2022
+++ src/sys/arch/aarch64/aarch64/cpu.c Thu Dec 22 06:58:07 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.70 2022/05/29 16:14:41 ryo Exp $ */
+/* $NetBSD: cpu.c,v 1.71 2022/12/22 06:58:07 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.70 2022/05/29 16:14:41 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.71 2022/12/22 06:58:07 ryo Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@@ -499,6 +499,7 @@ cpu_init_counter(struct cpu_info *ci)
}
reg_pmcr_el0_write(PMCR_E | PMCR_C);
+ reg_pmintenclr_el1_write(PMINTEN_C | PMINTEN_P);
reg_pmcntenset_el0_write(PMCNTEN_C);
const uint32_t prev = cpu_counter32();
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.184 src/sys/arch/arm/arm/cpufunc.c:1.185
--- src/sys/arch/arm/arm/cpufunc.c:1.184 Mon May 16 07:07:17 2022
+++ src/sys/arch/arm/arm/cpufunc.c Thu Dec 22 06:58:07 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.184 2022/05/16 07:07:17 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.185 2022/12/22 06:58:07 ryo Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.184 2022/05/16 07:07:17 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.185 2022/12/22 06:58:07 ryo Exp $");
#include "opt_arm_start.h"
#include "opt_compat_netbsd.h"
@@ -1964,6 +1964,7 @@ set_cpufuncs(void)
* Start and reset the PMC Cycle Counter.
*/
armreg_pmcr_write(ARM11_PMCCTL_E | ARM11_PMCCTL_P | ARM11_PMCCTL_C);
+ armreg_pmintenclr_write(PMINTEN_C | PMINTEN_P);
armreg_pmcntenset_write(CORTEX_CNTENS_C);
return 0;
}
Index: src/sys/arch/arm/arm32/arm32_boot.c
diff -u src/sys/arch/arm/arm32/arm32_boot.c:1.44 src/sys/arch/arm/arm32/arm32_boot.c:1.45
--- src/sys/arch/arm/arm32/arm32_boot.c:1.44 Sun Oct 31 16:23:47 2021
+++ src/sys/arch/arm/arm32/arm32_boot.c Thu Dec 22 06:58:08 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_boot.c,v 1.44 2021/10/31 16:23:47 skrll Exp $ */
+/* $NetBSD: arm32_boot.c,v 1.45 2022/12/22 06:58:08 ryo Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@@ -122,7 +122,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.44 2021/10/31 16:23:47 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.45 2022/12/22 06:58:08 ryo Exp $");
#include "opt_arm_debug.h"
#include "opt_cputypes.h"
@@ -407,6 +407,7 @@ cpu_hatch(struct cpu_info *ci, u_int cpu
* Start and reset the PMC Cycle Counter.
*/
armreg_pmcr_write(ARM11_PMCCTL_E|ARM11_PMCCTL_P|ARM11_PMCCTL_C);
+ armreg_pmintenclr_write(PMINTEN_C | PMINTEN_P);
armreg_pmcntenset_write(CORTEX_CNTENS_C);
}
#endif
