Module Name: src Committed By: skrll Date: Sat Oct 15 16:20:32 UTC 2022
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Remove unnecessary register assignments
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
