Module Name: src
Committed By: martin
Date: Sat Oct 15 10:16:08 UTC 2022
Modified Files:
src/sys/arch/x86/include [netbsd-8]: specialreg.h
src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1775):
sys/arch/x86/include/specialreg.h: revision 1.189
usr.sbin/cpuctl/arch/i386.c: revision 1.128
sys/arch/x86/include/specialreg.h: revision 1.190
sys/arch/x86/include/specialreg.h: revision 1.191
sys/arch/x86/include/specialreg.h: revision 1.192
s/shareing/sharing/. No functional change.
Add top-down slots event bit of architectural performance monitoring leaf.
Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.
Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>
Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
To generate a diff of this commit:
cvs rdiff -u -r1.98.2.23 -r1.98.2.24 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.74.6.14 -r1.74.6.15 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
