Module Name: src
Committed By: rin
Date: Sun Sep 4 13:14:57 UTC 2022
Modified Files:
src/sys/arch/powerpc/fpu: fpu_compare.c fpu_emu.c fpu_emu.h
fpu_implode.c
Log Message:
Fix logic for FI, FR, and FPRF fields of FPSCR.
They are not sticky bits and updated by arithmetic and round
insns at the same time.
Comparison insns update only FPCC sub-field of FPRF.
For other insns, these field are left untouched.
Also, for single-precision insns, exception bits should be set by
the first fpu_implode(), which rounds the value to float.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/powerpc/fpu/fpu_compare.c
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/powerpc/fpu/fpu_emu.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/powerpc/fpu/fpu_emu.h
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/powerpc/fpu/fpu_implode.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
