CVS commit: src/sys/arch/powerpc/fpu

[Rin Okuyama]

Module Name:    src
Committed By:   rin
Date:           Tue Aug 30 10:50:56 UTC 2022

Modified Files:
        src/sys/arch/powerpc/fpu: fpu_emu.c

Log Message:
Fix mtfsb[01]; these can clear/set any FPSCR bits other than FEX and VX.


To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/powerpc/fpu/fpu_emu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/powerpc/fpu/fpu_emu.c
diff -u src/sys/arch/powerpc/fpu/fpu_emu.c:1.38 src/sys/arch/powerpc/fpu/fpu_emu.c:1.39
--- src/sys/arch/powerpc/fpu/fpu_emu.c:1.38	Tue Aug 30 10:48:31 2022
+++ src/sys/arch/powerpc/fpu/fpu_emu.c	Tue Aug 30 10:50:56 2022
@@ -1,4 +1,4 @@
-/*	$NetBSD: fpu_emu.c,v 1.38 2022/08/30 10:48:31 rin Exp $ */
+/*	$NetBSD: fpu_emu.c,v 1.39 2022/08/30 10:50:56 rin Exp $ */
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -76,7 +76,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.38 2022/08/30 10:48:31 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.39 2022/08/30 10:50:56 rin Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_ddb.h"
@@ -289,7 +289,7 @@ fpu_execute(struct trapframe *tf, struct
 	int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr;
 	unsigned int cond;
 	struct fpreg *fs;
-	int mtfsf = 0;
+	int mtfsf = 0, mtfsb1 = 0;
 
 	/* Setup work. */
 	fp = NULL;
@@ -513,8 +513,9 @@ fpu_execute(struct trapframe *tf, struct
 			case	OPC63_MTFSB1:
 				FPU_EMU_EVCNT_INCR(mtfsb1);
 				DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n"));
-				fe->fe_fpscr |= 
-					(~(FPSCR_VX|FPSR_EX) & (1<<(31-rt)));
+				mtfsb1 = 1;
+				fe->fe_cx = (1 << (31 - rt)) &
+				    ~(FPSCR_FEX | FPSCR_VX);
 				break;
 			case	OPC63_FNEG:
 				FPU_EMU_EVCNT_INCR(fnegabs);
@@ -543,8 +544,8 @@ fpu_execute(struct trapframe *tf, struct
 			case	OPC63_MTFSB0:
 				FPU_EMU_EVCNT_INCR(mtfsb0);
 				DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n"));
-				fe->fe_fpscr &=
-					((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt)));
+				fe->fe_fpscr &= ~(1 << (31 - rt)) |
+				    (FPSCR_FEX | FPSCR_VX);
 				break;
 			case	OPC63_FMR:
 				FPU_EMU_EVCNT_INCR(fmr);
@@ -783,7 +784,7 @@ fpu_execute(struct trapframe *tf, struct
 	cx = fe->fe_cx;
 	fsr = fe->fe_fpscr & ~(FPSCR_FEX|FPSCR_VX);
 	if (cx != 0) {
-		if (cx & FPSCR_FPRF) {
+		if (mtfsb1 == 0 && (cx & FPSCR_FPRF) != 0) {
 			/* Need to replace CC */
 			fsr &= ~FPSCR_FPRF;
 		}