Module Name: src
Committed By: ryo
Date: Tue Aug 23 05:33:39 UTC 2022
Modified Files:
src/sys/arch/arm/rockchip: rk3399_cru.c rk_cru.h rk_cru_arm.c
Log Message:
- change struct rk_cru_arm and RK_CPU macros to allow mux and div registers to
be specified independently.
Allow more div-regs to be specified in the future.
- commonize RK*_PLL() macro.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/rockchip/rk3399_cru.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/rockchip/rk_cru.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rk_cru_arm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rk3399_cru.c
diff -u src/sys/arch/arm/rockchip/rk3399_cru.c:1.24 src/sys/arch/arm/rockchip/rk3399_cru.c:1.25
--- src/sys/arch/arm/rockchip/rk3399_cru.c:1.24 Tue Aug 23 05:32:18 2022
+++ src/sys/arch/arm/rockchip/rk3399_cru.c Tue Aug 23 05:33:39 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3399_cru.c,v 1.24 2022/08/23 05:32:18 ryo Exp $ */
+/* $NetBSD: rk3399_cru.c,v 1.25 2022/08/23 05:33:39 ryo Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.24 2022/08/23 05:32:18 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.25 2022/08/23 05:33:39 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -440,8 +440,9 @@ static struct rk_cru_clk rk3399_cru_clks
RK_GATE(0, "clk_core_l_gpll_src", "gpll", CLKGATE_CON(0), 3),
RK_CPU(RK3399_ARMCLKL, "armclkl", armclkl_parents,
- CLKSEL_CON(0), /* reg */
+ CLKSEL_CON(0), /* mux_reg */
__BITS(7,6), 0, 3, /* mux_mask, mux_main, mux_alt */
+ CLKSEL_CON(0), /* div_reg */
__BITS(4,0), /* div_mask */
armclkl_rates),
@@ -451,8 +452,9 @@ static struct rk_cru_clk rk3399_cru_clks
RK_GATE(0, "clk_core_b_gpll_src", "gpll", CLKGATE_CON(1), 3),
RK_CPU(RK3399_ARMCLKB, "armclkb", armclkb_parents,
- CLKSEL_CON(2), /* reg */
+ CLKSEL_CON(2), /* mux_reg */
__BITS(7,6), 1, 3, /* mux_mask, mux_main, mux_alt */
+ CLKSEL_CON(2), /* div_reg */
__BITS(4,0), /* div_mask */
armclkb_rates),
Index: src/sys/arch/arm/rockchip/rk_cru.h
diff -u src/sys/arch/arm/rockchip/rk_cru.h:1.9 src/sys/arch/arm/rockchip/rk_cru.h:1.10
--- src/sys/arch/arm/rockchip/rk_cru.h:1.9 Tue Aug 23 05:32:18 2022
+++ src/sys/arch/arm/rockchip/rk_cru.h Tue Aug 23 05:33:39 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: rk_cru.h,v 1.9 2022/08/23 05:32:18 ryo Exp $ */
+/* $NetBSD: rk_cru.h,v 1.10 2022/08/23 05:33:39 ryo Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
@@ -88,7 +88,7 @@ u_int rk_cru_pll_get_rate(struct rk_cru_
int rk_cru_pll_set_rate(struct rk_cru_softc *, struct rk_cru_clk *, u_int);
const char *rk_cru_pll_get_parent(struct rk_cru_softc *, struct rk_cru_clk *);
-#define RK_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
+#define RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, _flags) \
{ \
.id = (_id), \
.type = RK_CRU_PLL, \
@@ -102,31 +102,17 @@ const char *rk_cru_pll_get_parent(struct
.u.pll.lock_mask = (_lock_mask), \
.u.pll.rates = (_rates), \
.u.pll.nrates = __arraycount(_rates), \
- .u.pll.flags = 0, \
+ .u.pll.flags = _flags, \
.get_rate = rk_cru_pll_get_rate, \
.set_rate = rk_cru_pll_set_rate, \
.get_parent = rk_cru_pll_get_parent, \
}
+#define RK_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
+ RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, 0)
+
#define RK3288_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
- { \
- .id = (_id), \
- .type = RK_CRU_PLL, \
- .base.name = (_name), \
- .base.flags = 0, \
- .u.pll.parents = (_parents), \
- .u.pll.nparents = __arraycount(_parents), \
- .u.pll.con_base = (_con_base), \
- .u.pll.mode_reg = (_mode_reg), \
- .u.pll.mode_mask = (_mode_mask), \
- .u.pll.lock_mask = (_lock_mask), \
- .u.pll.rates = (_rates), \
- .u.pll.nrates = __arraycount(_rates), \
- .u.pll.flags = RK_PLL_RK3288, \
- .get_rate = rk_cru_pll_get_rate, \
- .set_rate = rk_cru_pll_set_rate, \
- .get_parent = rk_cru_pll_get_parent, \
- }
+ RK_PLL_FLAGS(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates, RK_PLL_RK3288)
/* ARM clocks */
@@ -152,12 +138,17 @@ struct rk_cru_cpu_rate {
struct rk_regmaskval divs[2];
};
-struct rk_cru_arm {
+struct rk_regmask {
bus_size_t reg;
+ uint32_t mask;
+};
+
+struct rk_cru_arm {
+ bus_size_t mux_reg;
uint32_t mux_mask;
u_int mux_main;
u_int mux_alt;
- uint32_t div_mask;
+ struct rk_regmask divs[1];
const char **parents;
u_int nparents;
const struct rk_cru_arm_rate *rates;
@@ -179,11 +170,12 @@ int rk_cru_arm_set_parent(struct rk_cru_
.base.flags = 0, \
.u.arm.parents = (_parents), \
.u.arm.nparents = __arraycount(_parents), \
- .u.arm.reg = (_reg), \
+ .u.arm.mux_reg = (_reg), \
.u.arm.mux_mask = (_mux_mask), \
.u.arm.mux_main = (_mux_main), \
.u.arm.mux_alt = (_mux_alt), \
- .u.arm.div_mask = (_div_mask), \
+ .u.arm.divs[0].reg = (_reg), \
+ .u.arm.divs[0].mask = (_div_mask), \
.u.arm.rates = (_rates), \
.u.arm.nrates = __arraycount(_rates), \
.get_rate = rk_cru_arm_get_rate, \
@@ -192,25 +184,32 @@ int rk_cru_arm_set_parent(struct rk_cru_
.set_parent = rk_cru_arm_set_parent, \
}
-#define RK_CPU(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _cpurates) \
- { \
- .id = (_id), \
- .type = RK_CRU_ARM, \
- .base.name = (_name), \
- .base.flags = 0, \
- .u.arm.parents = (_parents), \
- .u.arm.nparents = __arraycount(_parents), \
- .u.arm.reg = (_reg), \
- .u.arm.mux_mask = (_mux_mask), \
- .u.arm.mux_main = (_mux_main), \
- .u.arm.mux_alt = (_mux_alt), \
- .u.arm.div_mask = (_div_mask), \
- .u.arm.cpurates = (_cpurates), \
- .u.arm.nrates = __arraycount(_cpurates), \
- .get_rate = rk_cru_arm_get_rate, \
- .set_rate = rk_cru_arm_set_rate, \
- .get_parent = rk_cru_arm_get_parent, \
- .set_parent = rk_cru_arm_set_parent, \
+#define _RK_CPU_COMMON_INITIALIZER(_id, _name, _parents, \
+ _mux_reg, _mux_mask, _mux_main, _mux_alt, _cpurates) \
+ .id = (_id), \
+ .type = RK_CRU_ARM, \
+ .base.name = (_name), \
+ .base.flags = 0, \
+ .u.arm.parents = (_parents), \
+ .u.arm.nparents = __arraycount(_parents), \
+ .u.arm.mux_reg = (_mux_reg), \
+ .u.arm.mux_mask = (_mux_mask), \
+ .u.arm.mux_main = (_mux_main), \
+ .u.arm.mux_alt = (_mux_alt), \
+ .u.arm.cpurates = (_cpurates), \
+ .u.arm.nrates = __arraycount(_cpurates), \
+ .get_rate = rk_cru_arm_get_rate, \
+ .set_rate = rk_cru_arm_set_rate, \
+ .get_parent = rk_cru_arm_get_parent, \
+ .set_parent = rk_cru_arm_set_parent
+
+#define RK_CPU(_id, _name, _parents, _mux_reg, _mux_mask, _mux_main, _mux_alt, \
+ _div_reg, _div_mask, _cpurates) \
+ { \
+ _RK_CPU_COMMON_INITIALIZER(_id, _name, _parents, \
+ _mux_reg, _mux_mask, _mux_main, _mux_alt,_cpurates),\
+ .u.arm.divs[0].reg = (_div_reg), \
+ .u.arm.divs[0].mask = (_div_mask), \
}
/* Composite clocks */
Index: src/sys/arch/arm/rockchip/rk_cru_arm.c
diff -u src/sys/arch/arm/rockchip/rk_cru_arm.c:1.3 src/sys/arch/arm/rockchip/rk_cru_arm.c:1.4
--- src/sys/arch/arm/rockchip/rk_cru_arm.c:1.3 Tue Aug 23 05:32:18 2022
+++ src/sys/arch/arm/rockchip/rk_cru_arm.c Tue Aug 23 05:33:39 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: rk_cru_arm.c,v 1.3 2022/08/23 05:32:18 ryo Exp $ */
+/* $NetBSD: rk_cru_arm.c,v 1.4 2022/08/23 05:33:39 ryo Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rk_cru_arm.c,v 1.3 2022/08/23 05:32:18 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk_cru_arm.c,v 1.4 2022/08/23 05:33:39 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -54,8 +54,8 @@ rk_cru_arm_get_rate(struct rk_cru_softc
if (fref == 0)
return 0;
- const uint32_t val = CRU_READ(sc, arm->reg);
- const u_int div = __SHIFTOUT(val, arm->div_mask) + 1;
+ const uint32_t val = CRU_READ(sc, arm->divs[0].reg);
+ const u_int div = __SHIFTOUT(val, arm->divs[0].mask) + 1;
return fref / div;
}
@@ -99,10 +99,15 @@ rk_cru_arm_set_rate_rates(struct rk_cru_
if (error != 0)
goto done;
- const uint32_t write_mask = arm->div_mask << 16;
- const uint32_t write_val = __SHIFTIN(arm_rate->div - 1, arm->div_mask);
+ for (int i = 0; i < __arraycount(arm->divs); i++) {
+ if (arm->divs[i].reg == 0 && arm->divs[i].mask == 0)
+ break;
- CRU_WRITE(sc, arm->reg, write_mask | write_val);
+ const uint32_t write_mask = arm->divs[i].mask << 16;
+ const uint32_t write_val = __SHIFTIN(arm_rate->div - 1,
+ arm->divs[i].mask);
+ CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
+ }
done:
rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_main]);
@@ -148,14 +153,23 @@ rk_cru_arm_set_rate_cpurates(struct rk_c
goto done;
for (int i = 0; i < __arraycount(cpu_rate->divs); i++) {
+ if (cpu_rate->divs[i].reg == 0 && cpu_rate->divs[i].mask == 0 &&
+ cpu_rate->divs[i].val == 0)
+ break;
+
write_mask = cpu_rate->divs[i].mask << 16;
write_val = cpu_rate->divs[i].val;
CRU_WRITE(sc, cpu_rate->divs[i].reg, write_mask | write_val);
}
- write_mask = arm->div_mask << 16;
- write_val = __SHIFTIN(0, arm->div_mask);
- CRU_WRITE(sc, arm->reg, write_mask | write_val);
+ for (int i = 0; i < __arraycount(arm->divs); i++) {
+ if (arm->divs[i].reg == 0 && arm->divs[i].mask == 0)
+ break;
+
+ write_mask = arm->divs[i].mask << 16;
+ write_val = __SHIFTIN(0, arm->divs[i].mask);
+ CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
+ }
done:
rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_main]);
@@ -185,7 +199,7 @@ rk_cru_arm_get_parent(struct rk_cru_soft
KASSERT(clk->type == RK_CRU_ARM);
- const uint32_t val = CRU_READ(sc, arm->reg);
+ const uint32_t val = CRU_READ(sc, arm->mux_reg);
const u_int mux = __SHIFTOUT(val, arm->mux_mask);
return arm->parents[mux];
@@ -204,7 +218,7 @@ rk_cru_arm_set_parent(struct rk_cru_soft
const uint32_t write_mask = arm->mux_mask << 16;
const uint32_t write_val = __SHIFTIN(mux, arm->mux_mask);
- CRU_WRITE(sc, arm->reg, write_mask | write_val);
+ CRU_WRITE(sc, arm->mux_reg, write_mask | write_val);
return 0;
}
