Module Name: src
Committed By: rin
Date: Fri May 20 15:04:15 UTC 2022
Modified Files:
src/sys/arch/evbarm/marvell: marvell_start.S
Log Message:
Initial support for armv5eb on Sheeva.
Disable L2 cache for Sheeva before switch to big-endian mode.
Note that we need to encode this code sequence in little endian,
as u-boot starts kernel in little-endian mode.
XXX
At the moment, this code is unconditionally enabled if CPU_SHEEVA
option is enabled; it does not work for older CPUs.
It would be better to determine CPU type automatically as done for
little-endian variant, but it is too ugly to hand-assemble for
the opposite byte-order.
It may be nice if we have tools something like:
$ nbarm-elf-bswap -s marvell_start -e Lswitch_endian_done netbsd
Tested for OPENBLOCKS_A6 (for CPU_SHEEVA), as well as KUROBOX_PRO
(for !CPU_SHEEVA).
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/evbarm/marvell/marvell_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbarm/marvell/marvell_start.S
diff -u src/sys/arch/evbarm/marvell/marvell_start.S:1.11 src/sys/arch/evbarm/marvell/marvell_start.S:1.12
--- src/sys/arch/evbarm/marvell/marvell_start.S:1.11 Mon Aug 30 00:00:02 2021
+++ src/sys/arch/evbarm/marvell/marvell_start.S Fri May 20 15:04:15 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: marvell_start.S,v 1.11 2021/08/30 00:00:02 rin Exp $ */
+/* $NetBSD: marvell_start.S,v 1.12 2022/05/20 15:04:15 rin Exp $ */
/*
* Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
* All rights reserved.
@@ -66,7 +66,7 @@
#include <evbarm/marvell/marvellreg.h>
#include "assym.h"
-RCSID("$NetBSD: marvell_start.S,v 1.11 2021/08/30 00:00:02 rin Exp $")
+RCSID("$NetBSD: marvell_start.S,v 1.12 2022/05/20 15:04:15 rin Exp $")
#ifndef SDRAM_START
#define SDRAM_START 0x00000000
@@ -110,6 +110,22 @@ _C_LABEL(marvell_start):
* encode first few instructions in the opposite byte order.
*/
+#ifdef CPU_SHEEVA
+ /*
+ * XXX
+ * For now, disable L2 unconditionally ifdef CPU_SHEEVA.
+ * Not working for older CPUs.
+ */
+ .word 0x115f3fee /* mrc r15, 1, r5, r15, r1, 0 */
+ .word 0x0155c5e3 /* bic r5, r5, #0x400000 */
+ .word 0x115f2fee /* mcr r15, 1, r5, r15, r1, 0 */
+
+ /* Flush prefetch buffer. */
+ .word 0x0000a0e1 /* nop */
+ .word 0x0000a0e1 /* nop */
+ .word 0x0000a0e1 /* nop */
+#endif
+
/* Turn on CPU_CONTROL_BEND_ENABLE bit. */
.word 0x104f11ee /* mrc p15, 0, r4, c1, c0, 0 */
.word 0x804084e3 /* orr r4, r4, #CPU_CONTROL_BEND_ENABLE */
