Module Name: src
Committed By: msaitoh
Date: Sun Dec 5 07:56:10 UTC 2021
Modified Files:
src/crypto/dist/ipsec-tools/src/racoon: isakmp.c
src/sys/arch/arm/nvidia: tegra_hdmireg.h
src/sys/arch/arm/xscale: pxa2x0reg.h
src/sys/arch/sandpoint/stand/altboot: tlp.c
Log Message:
s/stauts/status/
To generate a diff of this commit:
cvs rdiff -u -r1.78 -r1.79 src/crypto/dist/ipsec-tools/src/racoon/isakmp.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/nvidia/tegra_hdmireg.h
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/xscale/pxa2x0reg.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/sandpoint/stand/altboot/tlp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/crypto/dist/ipsec-tools/src/racoon/isakmp.c
diff -u src/crypto/dist/ipsec-tools/src/racoon/isakmp.c:1.78 src/crypto/dist/ipsec-tools/src/racoon/isakmp.c:1.79
--- src/crypto/dist/ipsec-tools/src/racoon/isakmp.c:1.78 Sat May 19 20:14:56 2018
+++ src/crypto/dist/ipsec-tools/src/racoon/isakmp.c Sun Dec 5 07:56:10 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: isakmp.c,v 1.78 2018/05/19 20:14:56 maxv Exp $ */
+/* $NetBSD: isakmp.c,v 1.79 2021/12/05 07:56:10 msaitoh Exp $ */
/* Id: isakmp.c,v 1.74 2006/05/07 21:32:59 manubsd Exp */
@@ -687,7 +687,7 @@ isakmp_main(msg, remote, local)
return -1;
}
- /* search isakmp phase 2 stauts record. */
+ /* search isakmp phase 2 status record. */
iph2 = getph2bymsgid(iph1, msgid);
if (iph2 == NULL) {
/* it must be new negotiation as responder */
Index: src/sys/arch/arm/nvidia/tegra_hdmireg.h
diff -u src/sys/arch/arm/nvidia/tegra_hdmireg.h:1.5 src/sys/arch/arm/nvidia/tegra_hdmireg.h:1.6
--- src/sys/arch/arm/nvidia/tegra_hdmireg.h:1.5 Tue Nov 10 00:33:46 2015
+++ src/sys/arch/arm/nvidia/tegra_hdmireg.h Sun Dec 5 07:56:10 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_hdmireg.h,v 1.5 2015/11/10 00:33:46 jmcneill Exp $ */
+/* $NetBSD: tegra_hdmireg.h,v 1.6 2021/12/05 07:56:10 msaitoh Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -147,7 +147,7 @@
#define HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL __BITS(18,16)
#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1_REG 0x140
-#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STAUTS2_REG 0x144
+#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2_REG 0x144
#define HDMI_NV_PDISP_CRC_CONTROL_REG 0x258
#define HDMI_NV_PDISP_INPUT_CONTROL_REG 0x25c
Index: src/sys/arch/arm/xscale/pxa2x0reg.h
diff -u src/sys/arch/arm/xscale/pxa2x0reg.h:1.24 src/sys/arch/arm/xscale/pxa2x0reg.h:1.25
--- src/sys/arch/arm/xscale/pxa2x0reg.h:1.24 Wed Nov 10 16:22:44 2021
+++ src/sys/arch/arm/xscale/pxa2x0reg.h Sun Dec 5 07:56:10 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pxa2x0reg.h,v 1.24 2021/11/10 16:22:44 msaitoh Exp $ */
+/* $NetBSD: pxa2x0reg.h,v 1.25 2021/12/05 07:56:10 msaitoh Exp $ */
/*
* Copyright (c) 2002 Genetec Corporation. All rights reserved.
@@ -1005,7 +1005,7 @@ struct pxa2x0_dma_desc {
#define USBHC_UHCRHDB 0x004c /* UHC Root Hub Descriptor B */
#define UHCRHDB_PPCM(p) ((1<<(p))<<16) /* Port Power Control Mask [1:3] */
#define UHCRHDB_DNR(p) ((1<<(p))<<0) /* Device Not Removable [1:3] */
-#define USBHC_UHCRHS 0x0050 /* UHC Root Hub Stauts */
+#define USBHC_UHCRHS 0x0050 /* UHC Root Hub Status */
#define USBHC_UHCHR 0x0064 /* UHC Reset Register */
#define UHCHR_SSEP3 (1<<11) /* Sleep standby enable for port3 */
#define UHCHR_SSEP2 (1<<10) /* Sleep standby enable for port2 */
Index: src/sys/arch/sandpoint/stand/altboot/tlp.c
diff -u src/sys/arch/sandpoint/stand/altboot/tlp.c:1.2 src/sys/arch/sandpoint/stand/altboot/tlp.c:1.3
--- src/sys/arch/sandpoint/stand/altboot/tlp.c:1.2 Fri Dec 27 09:41:49 2019
+++ src/sys/arch/sandpoint/stand/altboot/tlp.c Sun Dec 5 07:56:10 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: tlp.c,v 1.2 2019/12/27 09:41:49 msaitoh Exp $ */
+/* $NetBSD: tlp.c,v 1.3 2021/12/05 07:56:10 msaitoh Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -79,7 +79,7 @@ struct desc {
#define RDR_CSR2 0x10 /* R0_OWN poll demand */
#define RDB_CSR3 0x18 /* Rx descriptor base */
#define TDB_CSR4 0x20 /* Tx descriptor base */
-#define SR_CSR5 0x28 /* interrupt stauts */
+#define SR_CSR5 0x28 /* interrupt status */
#define NAR_CSR6 0x30 /* operation mode */
#define NAR_NOSQE (1U<<19) /* _not_ use SQE signal */
#define NAR_TEN (1U<<13) /* instruct start/stop Tx */
