Module Name: src
Committed By: msaitoh
Date: Sun Oct 10 23:28:36 UTC 2021
Modified Files:
src/sys/dev/pci: pci.c pci_subr.c pcireg.h ppb.c
Log Message:
Use PCI-SIG official acronyms:
- RP stands for Root Port.
- RC stands for Root Complex.
- RCIEP stands for Root Complex Integrated End Point.
To generate a diff of this commit:
cvs rdiff -u -r1.162 -r1.163 src/sys/dev/pci/pci.c
cvs rdiff -u -r1.231 -r1.232 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.160 -r1.161 src/sys/dev/pci/pcireg.h
cvs rdiff -u -r1.73 -r1.74 src/sys/dev/pci/ppb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci.c
diff -u src/sys/dev/pci/pci.c:1.162 src/sys/dev/pci/pci.c:1.163
--- src/sys/dev/pci/pci.c:1.162 Wed Sep 15 17:33:08 2021
+++ src/sys/dev/pci/pci.c Sun Oct 10 23:28:36 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pci.c,v 1.162 2021/09/15 17:33:08 thorpej Exp $ */
+/* $NetBSD: pci.c,v 1.163 2021/10/10 23:28:36 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1997, 1998
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.162 2021/09/15 17:33:08 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.163 2021/10/10 23:28:36 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -735,7 +735,7 @@ pci_enumerate_bus(struct pci_softc *sc,
if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS,
&pciecap, &capreg) != 0) {
switch (PCIE_XCAP_TYPE(capreg)) {
- case PCIE_XCAP_TYPE_ROOT:
+ case PCIE_XCAP_TYPE_RP:
case PCIE_XCAP_TYPE_DOWN:
case PCIE_XCAP_TYPE_PCI2PCIE:
downstream_port = true;
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.231 src/sys/dev/pci/pci_subr.c:1.232
--- src/sys/dev/pci/pci_subr.c:1.231 Sun Oct 10 07:20:01 2021
+++ src/sys/dev/pci/pci_subr.c Sun Oct 10 23:28:36 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.231 2021/10/10 07:20:01 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.232 2021/10/10 23:28:36 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.231 2021/10/10 07:20:01 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.232 2021/10/10 23:28:36 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -914,7 +914,7 @@ pci_conf_print_common(
if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
reg = regs[o2i(pcie_capoff + PCIE_XCAP)];
- if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC)
+ if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC)
subclass = PCI_SUBCLASS_SYSTEM_RCEC;
}
}
@@ -1861,7 +1861,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
printf("Legacy PCI Express Endpoint device\n");
check_upstreamport = true;
break;
- case PCIE_XCAP_TYPE_ROOT: /* 0x4 */
+ case PCIE_XCAP_TYPE_RP: /* 0x4 */
printf("Root Port of PCI Express Root Complex\n");
check_slot = true;
break;
@@ -1882,10 +1882,10 @@ pci_conf_print_pcie_cap(const pcireg_t *
/* Upstream port is not PCIe */
check_slot = true;
break;
- case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */
+ case PCIE_XCAP_TYPE_RCIEP: /* 0x9 */
printf("Root Complex Integrated Endpoint\n");
break;
- case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */
+ case PCIE_XCAP_TYPE_RC_EVNTC: /* 0xa */
printf("Root Complex Event Collector\n");
break;
default:
@@ -2930,8 +2930,8 @@ pci_conf_print_aer_cap(const pcireg_t *r
extcapoff + PCI_AER_ROOTERR_CMD);
switch (pcie_devtype) {
- case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */
- case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */
+ case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */
+ case PCIE_XCAP_TYPE_RC_EVNTC: /* Root Complex Event Collector */
reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];
printf(" Root Error Command register: 0x%08x\n", reg);
pci_conf_print_aer_cap_rooterr_cmd(reg);
@@ -4149,7 +4149,7 @@ pci_conf_print_l1pm_cap(const pcireg_t *
if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
uint32_t t = regs[o2i(pcie_capoff)];
- if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN))
+ if ((t == PCIE_XCAP_TYPE_RP) || (t == PCIE_XCAP_TYPE_DOWN))
onoff("Link Activation Supported", reg,
PCI_L1PM_CAP_LA);
}
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.160 src/sys/dev/pci/pcireg.h:1.161
--- src/sys/dev/pci/pcireg.h:1.160 Sun Oct 10 07:20:01 2021
+++ src/sys/dev/pci/pcireg.h Sun Oct 10 23:28:36 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.160 2021/10/10 07:20:01 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.161 2021/10/10 23:28:36 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -983,13 +983,13 @@ typedef u_int8_t pci_revision_t;
#define PCIE_XCAP_TYPE(x) __SHIFTOUT((x), PCIE_XCAP_TYPE_MASK)
#define PCIE_XCAP_TYPE_PCIE_DEV 0x0
#define PCIE_XCAP_TYPE_PCI_DEV 0x1
-#define PCIE_XCAP_TYPE_ROOT 0x4
+#define PCIE_XCAP_TYPE_RP 0x4
#define PCIE_XCAP_TYPE_UP 0x5
#define PCIE_XCAP_TYPE_DOWN 0x6
#define PCIE_XCAP_TYPE_PCIE2PCI 0x7
#define PCIE_XCAP_TYPE_PCI2PCIE 0x8
-#define PCIE_XCAP_TYPE_ROOT_INTEP 0x9
-#define PCIE_XCAP_TYPE_ROOT_EVNTC 0xa
+#define PCIE_XCAP_TYPE_RCIEP 0x9
+#define PCIE_XCAP_TYPE_RC_EVNTC 0xa
#define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */
#define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK)
#define PCIE_DCAP 0x04 /* Device Capabilities Register */
@@ -1198,12 +1198,12 @@ typedef u_int8_t pci_revision_t;
* Other than Root Complex Integrated Endpoint and Root Complex Event Collector
* have link related registers.
*/
-#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_ROOT_INTEP) && \
- ((type) != PCIE_XCAP_TYPE_ROOT_EVNTC))
+#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_RCIEP) && \
+ ((type) != PCIE_XCAP_TYPE_RC_EVNTC))
/* Only root port and root complex event collector have PCIE_RCR & PCIE_RSR */
-#define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_ROOT) || \
- ((type) == PCIE_XCAP_TYPE_ROOT_EVNTC))
+#define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_RP) || \
+ ((type) == PCIE_XCAP_TYPE_RC_EVNTC))
/*
Index: src/sys/dev/pci/ppb.c
diff -u src/sys/dev/pci/ppb.c:1.73 src/sys/dev/pci/ppb.c:1.74
--- src/sys/dev/pci/ppb.c:1.73 Sat Aug 7 16:19:14 2021
+++ src/sys/dev/pci/ppb.c Sun Oct 10 23:28:36 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: ppb.c,v 1.73 2021/08/07 16:19:14 thorpej Exp $ */
+/* $NetBSD: ppb.c,v 1.74 2021/10/10 23:28:36 msaitoh Exp $ */
/*
* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.73 2021/08/07 16:19:14 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.74 2021/10/10 23:28:36 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_ppb.h"
@@ -146,7 +146,7 @@ ppb_print_pcie(device_t self)
case PCIE_XCAP_TYPE_PCI_DEV:
aprint_normal("Legacy PCI-E Endpoint device");
break;
- case PCIE_XCAP_TYPE_ROOT:
+ case PCIE_XCAP_TYPE_RP:
aprint_normal("Root Port of PCI-E Root Complex");
break;
case PCIE_XCAP_TYPE_UP:
@@ -167,7 +167,7 @@ ppb_print_pcie(device_t self)
}
switch (devtype) {
- case PCIE_XCAP_TYPE_ROOT:
+ case PCIE_XCAP_TYPE_RP:
case PCIE_XCAP_TYPE_DOWN:
case PCIE_XCAP_TYPE_PCI2PCIE:
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCAP);
