Module Name: src
Committed By: martin
Date: Mon Nov 25 16:53:55 UTC 2019
Modified Files:
src/sys/dev/mii [netbsd-9]: files.mii miidevs.h miidevs_data.h
Added Files:
src/sys/dev/mii [netbsd-9]: jmphy.c jmphyreg.h smscphy.c
Log Message:
Regen for ticket 479
To generate a diff of this commit:
cvs rdiff -u -r1.50.26.1 -r1.50.26.2 src/sys/dev/mii/files.mii
cvs rdiff -u -r0 -r1.1.2.2 src/sys/dev/mii/jmphy.c src/sys/dev/mii/jmphyreg.h \
src/sys/dev/mii/smscphy.c
cvs rdiff -u -r1.151.2.3 -r1.151.2.4 src/sys/dev/mii/miidevs.h
cvs rdiff -u -r1.139.2.3 -r1.139.2.4 src/sys/dev/mii/miidevs_data.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/files.mii
diff -u src/sys/dev/mii/files.mii:1.50.26.1 src/sys/dev/mii/files.mii:1.50.26.2
--- src/sys/dev/mii/files.mii:1.50.26.1 Mon Nov 25 16:44:31 2019
+++ src/sys/dev/mii/files.mii Mon Nov 25 16:53:55 2019
@@ -1,4 +1,4 @@
-# $NetBSD: files.mii,v 1.50.26.1 2019/11/25 16:44:31 martin Exp $
+# $NetBSD: files.mii,v 1.50.26.2 2019/11/25 16:53:55 martin Exp $
defflag opt_mii.h MIIVERBOSE
@@ -103,6 +103,10 @@ device ipgphy: mii_phy
attach ipgphy at mii
file dev/mii/ipgphy.c ipgphy
+device jmphy: mii_phy
+attach jmphy at mii
+file dev/mii/jmphy.c jmphy
+
device sqphy: mii_phy
attach sqphy at mii
file dev/mii/sqphy.c sqphy
@@ -162,3 +166,7 @@ file dev/mii/rdcphy.c rdcphy
device micphy: mii_phy, ukphy_subr
attach micphy at mii
file dev/mii/micphy.c micphy
+
+device smscphy: mii_phy
+attach smscphy at mii
+file dev/mii/smscphy.c smscphy
Index: src/sys/dev/mii/miidevs.h
diff -u src/sys/dev/mii/miidevs.h:1.151.2.3 src/sys/dev/mii/miidevs.h:1.151.2.4
--- src/sys/dev/mii/miidevs.h:1.151.2.3 Mon Nov 25 16:26:31 2019
+++ src/sys/dev/mii/miidevs.h Mon Nov 25 16:53:55 2019
@@ -1,10 +1,10 @@
-/* $NetBSD: miidevs.h,v 1.151.2.3 2019/11/25 16:26:31 martin Exp $ */
+/* $NetBSD: miidevs.h,v 1.151.2.4 2019/11/25 16:53:55 martin Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: miidevs,v 1.153.2.3 2019/11/25 16:26:00 martin Exp
+ * NetBSD: miidevs,v 1.153.2.4 2019/11/25 16:53:29 martin Exp
*/
/*-
@@ -494,13 +494,27 @@
#define MII_MODEL_MARVELL_E1111 0x000c
#define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
-/* Micrel PHYs */
+/* Micrel PHYs (Kendin and Microchip) */
+#define MII_MODEL_MICREL_KSZ8041 0x0011
+#define MII_STR_MICREL_KSZ8041 "Micrel KSZ8041TL/FTL/MLL 10/100 PHY"
+#define MII_MODEL_MICREL_KSZ8041RNLI 0x0013
+#define MII_STR_MICREL_KSZ8041RNLI "Micrel KSZ8041RNLI 10/100 PHY"
+#define MII_MODEL_MICREL_KSZ8051 0x0015
+#define MII_STR_MICREL_KSZ8051 "Micrel KSZ80[235]1 10/100 PHY"
#define MII_MODEL_MICREL_KSZ8081 0x0016
-#define MII_STR_MICREL_KSZ8081 "Micrel KSZ8081 10/100 PHY"
-#define MII_MODEL_MICREL_KSZ9021RNI 0x0021
-#define MII_STR_MICREL_KSZ9021RNI "Micrel KSZ9021RNI 10/100/1000 PHY"
+#define MII_STR_MICREL_KSZ8081 "Micrel KSZ80[89]1 10/100 PHY"
+#define MII_MODEL_MICREL_KSZ8061 0x0017
+#define MII_STR_MICREL_KSZ8061 "Micrel KSZ8061 10/100 PHY"
+#define MII_MODEL_MICREL_KSZ9021_8001_8721 0x0021
+#define MII_STR_MICREL_KSZ9021_8001_8721 "Micrel KSZ9021 Gb & KSZ8001/8721 10/100 PHY"
#define MII_MODEL_MICREL_KSZ9031 0x0022
#define MII_STR_MICREL_KSZ9031 "Micrel KSZ9031 10/100/1000 PHY"
+#define MII_MODEL_MICREL_KSZ9477 0x0023
+#define MII_STR_MICREL_KSZ9477 "Micrel KSZ9477 10/100/1000 PHY"
+#define MII_MODEL_MICREL_KSZ9131 0x0024
+#define MII_STR_MICREL_KSZ9131 "Micrel KSZ9131 10/100/1000 PHY"
+#define MII_MODEL_MICREL_KS8737 0x0032
+#define MII_STR_MICREL_KS8737 "Micrel KS8737 10/100 PHY"
/* Myson Technology PHYs */
#define MII_MODEL_xxMYSON_MTD972 0x0000
Index: src/sys/dev/mii/miidevs_data.h
diff -u src/sys/dev/mii/miidevs_data.h:1.139.2.3 src/sys/dev/mii/miidevs_data.h:1.139.2.4
--- src/sys/dev/mii/miidevs_data.h:1.139.2.3 Mon Nov 25 16:26:31 2019
+++ src/sys/dev/mii/miidevs_data.h Mon Nov 25 16:53:55 2019
@@ -1,10 +1,10 @@
-/* $NetBSD: miidevs_data.h,v 1.139.2.3 2019/11/25 16:26:31 martin Exp $ */
+/* $NetBSD: miidevs_data.h,v 1.139.2.4 2019/11/25 16:53:55 martin Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: miidevs,v 1.153.2.3 2019/11/25 16:26:00 martin Exp
+ * NetBSD: miidevs,v 1.153.2.4 2019/11/25 16:53:29 martin Exp
*/
/*-
@@ -204,9 +204,16 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_5, MII_STR_MARVELL_E1000_5 },
{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_6, MII_STR_MARVELL_E1000_6 },
{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1111, MII_STR_MARVELL_E1111 },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ8041, MII_STR_MICREL_KSZ8041 },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ8041RNLI, MII_STR_MICREL_KSZ8041RNLI },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ8051, MII_STR_MICREL_KSZ8051 },
{ MII_OUI_MICREL, MII_MODEL_MICREL_KSZ8081, MII_STR_MICREL_KSZ8081 },
- { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ9021RNI, MII_STR_MICREL_KSZ9021RNI },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ8061, MII_STR_MICREL_KSZ8061 },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ9021_8001_8721, MII_STR_MICREL_KSZ9021_8001_8721 },
{ MII_OUI_MICREL, MII_MODEL_MICREL_KSZ9031, MII_STR_MICREL_KSZ9031 },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ9477, MII_STR_MICREL_KSZ9477 },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ9131, MII_STR_MICREL_KSZ9131 },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KS8737, MII_STR_MICREL_KS8737 },
{ MII_OUI_xxMYSON, MII_MODEL_xxMYSON_MTD972, MII_STR_xxMYSON_MTD972 },
{ MII_OUI_MYSON, MII_MODEL_MYSON_MTD803, MII_STR_MYSON_MTD803 },
{ MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 },
Added files:
Index: src/sys/dev/mii/jmphy.c
diff -u /dev/null src/sys/dev/mii/jmphy.c:1.1.2.2
--- /dev/null Mon Nov 25 16:53:55 2019
+++ src/sys/dev/mii/jmphy.c Mon Nov 25 16:53:55 2019
@@ -0,0 +1,358 @@
+/* $NetBSD: jmphy.c,v 1.1.2.2 2019/11/25 16:53:55 martin Exp $ */
+/* $OpenBSD: jmphy.c,v 1.6 2015/03/14 03:38:48 jsg Exp $ */
+/*-
+ * Copyright (c) 2008, Pyun YongHyeon <yong...@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/mii/jmphy.c,v 1.1 2008/05/27 01:16:40 yongari Exp $
+ * $DragonFly: src/sys/dev/netif/mii_layer/jmphy.c,v 1.1 2008/07/22 11:28:49 sephe Exp $
+ */
+
+/*
+ * Driver for the JMicron JMP211 10/100/1000, JMP202 10/100 PHY.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+#include <dev/mii/jmphyreg.h>
+
+static int jmphy_service(struct mii_softc *, struct mii_data *, int);
+static void jmphy_status(struct mii_softc *);
+static int jmphy_match(device_t, cfdata_t, void *);
+static void jmphy_attach(device_t, device_t, void *);
+static void jmphy_reset(struct mii_softc *);
+static uint16_t jmphy_anar(struct ifmedia_entry *);
+static int jmphy_auto(struct mii_softc *, struct ifmedia_entry *);
+
+static const struct mii_phy_funcs jmphy_funcs = {
+ jmphy_service, jmphy_status, jmphy_reset,
+};
+
+CFATTACH_DECL_NEW(jmphy, sizeof (struct mii_softc),
+ jmphy_match, jmphy_attach, mii_phy_detach, mii_phy_activate);
+
+static const struct mii_phydesc jmphys[] = {
+ MII_PHY_DESC(JMICRON, JMP202),
+ MII_PHY_DESC(JMICRON, JMP211),
+ MII_PHY_END,
+};
+
+static int
+jmphy_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct mii_attach_args *ma = aux;
+
+ if (mii_phy_match(ma, jmphys) != NULL)
+ return 10;
+
+ return 0;
+}
+
+static void
+jmphy_attach(device_t parent, device_t self, void *aux)
+{
+ struct mii_softc *sc = device_private(self);
+ struct mii_attach_args *ma = aux;
+ struct mii_data *mii = ma->mii_data;
+ const struct mii_phydesc *mpd;
+
+ mpd = mii_phy_match(ma, jmphys);
+ aprint_naive(": Media interface\n");
+ aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
+
+ sc->mii_dev = self;
+ sc->mii_inst = mii->mii_instance;
+ sc->mii_phy = ma->mii_phyno;
+ sc->mii_funcs = &jmphy_funcs;
+ sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
+ sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
+ sc->mii_mpd_rev = MII_REV(ma->mii_id2);
+ sc->mii_pdata = mii;
+ sc->mii_flags = ma->mii_flags;
+
+ sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
+
+ PHY_RESET(sc);
+
+ PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
+ sc->mii_capabilities &= ma->mii_capmask;
+ if (sc->mii_capabilities & BMSR_EXTSTAT)
+ PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
+
+ aprint_normal_dev(self, "");
+ if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
+ (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
+ aprint_error("no media present");
+ else
+ mii_phy_add_media(sc);
+ aprint_normal("\n");
+}
+
+static int
+jmphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
+ struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+ uint16_t bmcr, ssr;
+
+ switch (cmd) {
+ case MII_POLLSTAT:
+ /*
+ * If we're not polling our PHY instance, just return.
+ */
+ if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+ return 0;
+ break;
+
+ case MII_MEDIACHG:
+ /*
+ * If the media indicates a different PHY instance,
+ * isolate ourselves.
+ */
+ if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
+ PHY_READ(sc, MII_BMCR, &bmcr);
+ PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
+ return 0;
+ }
+
+ /*
+ * If the interface is not up, don't do anything.
+ */
+ if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+ break;
+
+ if (jmphy_auto(sc, ife) != EJUSTRETURN)
+ return EINVAL;
+ break;
+
+ case MII_TICK:
+ /*
+ * If we're not currently selected, just return.
+ */
+ if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+ return 0;
+
+ /*
+ * Is the interface even up?
+ */
+ if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+ return 0;
+
+ /*
+ * Only used for autonegotiation.
+ */
+ if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
+ break;
+
+ /* Check for link. */
+ PHY_READ(sc, JMPHY_SSR, &ssr);
+ if (ssr & JMPHY_SSR_LINK_UP) {
+ sc->mii_ticks = 0;
+ break;
+ }
+
+ /* Announce link loss right after it happens. */
+ if (sc->mii_ticks++ == 0)
+ break;
+ if (sc->mii_ticks <= sc->mii_anegticks)
+ return 0;
+
+ sc->mii_ticks = 0;
+ jmphy_auto(sc, ife);
+ break;
+ }
+
+ /* Update the media status. */
+ jmphy_status(sc);
+
+ /* Callback if something changed. */
+ mii_phy_update(sc, cmd);
+ return 0;
+}
+
+static void
+jmphy_status(struct mii_softc *sc)
+{
+ struct mii_data *mii = sc->mii_pdata;
+ uint16_t bmcr, ssr, gtsr;
+
+ mii->mii_media_status = IFM_AVALID;
+ mii->mii_media_active = IFM_ETHER;
+
+ PHY_READ(sc, JMPHY_SSR, &ssr);
+ if ((ssr & JMPHY_SSR_LINK_UP) != 0)
+ mii->mii_media_status |= IFM_ACTIVE;
+
+ PHY_READ(sc, MII_BMCR, &bmcr);
+ if ((bmcr & BMCR_ISO) != 0) {
+ mii->mii_media_active |= IFM_NONE;
+ mii->mii_media_status = 0;
+ return;
+ }
+
+ if ((bmcr & BMCR_LOOP) != 0)
+ mii->mii_media_active |= IFM_LOOP;
+
+ if ((ssr & JMPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
+ /* Erg, still trying, I guess... */
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ }
+
+ switch ((ssr & JMPHY_SSR_SPEED_MASK)) {
+ case JMPHY_SSR_SPEED_1000:
+ mii->mii_media_active |= IFM_1000_T;
+ /*
+ * jmphy(4) got a valid link so reset mii_ticks.
+ * Resetting mii_ticks is needed in order to
+ * detect link loss after auto-negotiation.
+ */
+ sc->mii_ticks = 0;
+ break;
+ case JMPHY_SSR_SPEED_100:
+ mii->mii_media_active |= IFM_100_TX;
+ sc->mii_ticks = 0;
+ break;
+ case JMPHY_SSR_SPEED_10:
+ mii->mii_media_active |= IFM_10_T;
+ sc->mii_ticks = 0;
+ break;
+ default:
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ }
+
+ if ((ssr & JMPHY_SSR_DUPLEX) != 0)
+ mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
+ else
+ mii->mii_media_active |= IFM_HDX;
+
+ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
+ PHY_READ(sc, MII_GTSR, >sr);
+ if ((gtsr & GTSR_MS_RES) != 0)
+ mii->mii_media_active |= IFM_ETH_MASTER;
+ }
+}
+
+static void
+jmphy_reset(struct mii_softc *sc)
+{
+ int i;
+ uint16_t val;
+
+ /* Disable sleep mode. */
+ PHY_READ(sc, JMPHY_TMCTL, &val);
+ PHY_WRITE(sc, JMPHY_TMCTL, val & ~JMPHY_TMCTL_SLEEP_ENB);
+
+ PHY_READ(sc, MII_BMCR, &val);
+ PHY_WRITE(sc, MII_BMCR, val | BMCR_RESET);
+
+ for (i = 0; i < 1000; i++) {
+ DELAY(1);
+ PHY_READ(sc, MII_BMCR, &val);
+ if ((val & BMCR_RESET) == 0)
+ break;
+ }
+}
+
+static uint16_t
+jmphy_anar(struct ifmedia_entry *ife)
+{
+ uint16_t anar;
+
+ anar = 0;
+ switch (IFM_SUBTYPE(ife->ifm_media)) {
+ case IFM_AUTO:
+ anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
+ break;
+ case IFM_1000_T:
+ break;
+ case IFM_100_TX:
+ anar |= ANAR_TX | ANAR_TX_FD;
+ break;
+ case IFM_10_T:
+ anar |= ANAR_10 | ANAR_10_FD;
+ break;
+ default:
+ break;
+ }
+
+ return anar;
+}
+
+static int
+jmphy_auto(struct mii_softc *sc, struct ifmedia_entry *ife)
+{
+ uint16_t anar, bmcr, gig;
+
+ gig = 0;
+ PHY_READ(sc, MII_BMCR, &bmcr);
+ switch (IFM_SUBTYPE(ife->ifm_media)) {
+ case IFM_AUTO:
+ gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
+ break;
+ case IFM_1000_T:
+ gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
+ break;
+ case IFM_100_TX:
+ case IFM_10_T:
+ break;
+ case IFM_NONE:
+ PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO | BMCR_PDOWN);
+ return EJUSTRETURN;
+ default:
+ return EINVAL;
+ }
+
+ if ((ife->ifm_media & IFM_LOOP) != 0)
+ bmcr |= BMCR_LOOP;
+
+ anar = jmphy_anar(ife);
+ if (sc->mii_flags & MIIF_DOPAUSE)
+ anar |= ANAR_PAUSE_TOWARDS;
+
+ if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
+#ifdef notyet
+ struct mii_data *mii;
+
+ mii = sc->mii_pdata;
+ if ((mii->mii_media.ifm_media & IFM_ETH_MASTER) != 0)
+ gig |= GTCR_MAN_MS | GTCR_MAN_ADV;
+#endif
+ PHY_WRITE(sc, MII_100T2CR, gig);
+ }
+ PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
+ PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
+
+ return EJUSTRETURN;
+}
Index: src/sys/dev/mii/jmphyreg.h
diff -u /dev/null src/sys/dev/mii/jmphyreg.h:1.1.2.2
--- /dev/null Mon Nov 25 16:53:55 2019
+++ src/sys/dev/mii/jmphyreg.h Mon Nov 25 16:53:55 2019
@@ -0,0 +1,116 @@
+/* $NetBSD: jmphyreg.h,v 1.1.2.2 2019/11/25 16:53:55 martin Exp $ */
+/* $OpenBSD: jmphyreg.h,v 1.1 2008/09/26 10:35:15 jsg Exp $ */
+/*-
+ * Copyright (c) 2008, Pyun YongHyeon
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/mii/jmphyreg.h,v 1.1 2008/05/27 01:16:40 yongari Exp $
+ * $DragonFly: src/sys/dev/netif/mii_layer/jmphyreg.h,v 1.2 2008/09/13 04:04:39 sephe Exp $
+ */
+
+#ifndef _DEV_MII_JMPHYREG_H_
+#define _DEV_MII_JMPHYREG_H_
+
+/*
+ * Registers for the JMicron JMC250 Gigabit PHY.
+ */
+
+/* PHY specific status register. */
+#define JMPHY_SSR 0x11
+#define JMPHY_SSR_SPEED_1000 0x8000
+#define JMPHY_SSR_SPEED_100 0x4000
+#define JMPHY_SSR_SPEED_10 0x0000
+#define JMPHY_SSR_SPEED_MASK 0xC000
+#define JMPHY_SSR_DUPLEX 0x2000
+#define JMPHY_SSR_SPD_DPLX_RESOLVED 0x0800
+#define JMPHY_SSR_LINK_UP 0x0400
+#define JMPHY_SSR_MDI_XOVER 0x0040
+#define JMPHY_SSR_INV_POLARITY 0x0002
+
+/* PHY specific cable length status register. */
+#define JMPHY_SCL 0x17
+#define JMPHY_SCL_CHAN_D_MASK 0xF000
+#define JMPHY_SCL_CHAN_C_MASK 0x0F00
+#define JMPHY_SCL_CHAN_B_MASK 0x00F0
+#define JMPHY_SCL_CHAN_A_MASK 0x000F
+#define JMPHY_SCL_LEN_35 0
+#define JMPHY_SCL_LEN_40 1
+#define JMPHY_SCL_LEN_50 2
+#define JMPHY_SCL_LEN_60 3
+#define JMPHY_SCL_LEN_70 4
+#define JMPHY_SCL_LEN_80 5
+#define JMPHY_SCL_LEN_90 6
+#define JMPHY_SCL_LEN_100 7
+#define JMPHY_SCL_LEN_110 8
+#define JMPHY_SCL_LEN_120 9
+#define JMPHY_SCL_LEN_130 10
+#define JMPHY_SCL_LEN_140 11
+#define JMPHY_SCL_LEN_150 12
+#define JMPHY_SCL_LEN_160 13
+#define JMPHY_SCL_LEN_170 14
+#define JMPHY_SCL_RSVD 15
+
+/* PHY specific LED control register 1. */
+#define JMPHY_LED_CTL1 0x18
+#define JMPHY_LED_BLINK_42MS 0x0000
+#define JMPHY_LED_BLINK_84MS 0x2000
+#define JMPHY_LED_BLINK_170MS 0x4000
+#define JMPHY_LED_BLINK_340MS 0x6000
+#define JMPHY_LED_BLINK_670MS 0x8000
+#define JMPHY_LED_BLINK_MASK 0xE000
+#define JMPHY_LED_FLP_GAP_MASK 0x1F00
+#define JMPHY_LED_FLP_GAP_DEFULT 0x1000
+#define JMPHY_LED2_POLARITY_MASK 0x0030
+#define JMPHY_LED1_POLARITY_MASK 0x000C
+#define JMPHY_LED0_POLARITY_MASK 0x0003
+#define JMPHY_LED_ON_LO_OFF_HI 0
+#define JMPHY_LED_ON_HI_OFF_HI 1
+#define JMPHY_LED_ON_LO_OFF_TS 2
+#define JMPHY_LED_ON_HI_OFF_TS 3
+
+/* PHY specific LED control register 2. */
+#define JMPHY_LED_CTL2 0x19
+#define JMPHY_LED_NO_STRETCH 0x0000
+#define JMPHY_LED_STRETCH_42MS 0x2000
+#define JMPHY_LED_STRETCH_84MS 0x4000
+#define JMPHY_LED_STRETCH_170MS 0x6000
+#define JMPHY_LED_STRETCH_340MS 0x8000
+#define JMPHY_LED_STRETCH_670MS 0xB000
+#define JMPHY_LED_STRETCH_1300MS 0xC000
+#define JMPHY_LED_STRETCH_2700MS 0xE000
+#define JMPHY_LED2_MODE_MASK 0x0F00
+#define JMPHY_LED1_MODE_MASK 0x00F0
+#define JMPHY_LED0_MODE_MASK 0x000F
+
+/* PHY specific test mode control register. */
+#define JMPHY_TMCTL 0x1A
+#define JMPHY_TMCTL_SLEEP_ENB 0x1000
+
+/* PHY specific configuration */
+#define JMPHY_CONF 0x1B
+#define JMPHY_CONF_EXTFIFO 0x0000 /* use extended fifo */
+#define JMPHY_CONF_DEFFIFO 0x0004 /* use default fifo */
+
+#endif /* _DEV_MII_JMPHYREG_H_ */
Index: src/sys/dev/mii/smscphy.c
diff -u /dev/null src/sys/dev/mii/smscphy.c:1.1.2.2
--- /dev/null Mon Nov 25 16:53:55 2019
+++ src/sys/dev/mii/smscphy.c Mon Nov 25 16:53:55 2019
@@ -0,0 +1,251 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2006 Benno Rice. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+/* $FreeBSD: head/sys/dev/mii/smscphy.c 326255 2017-11-27 14:52:40Z pfg $ */
+
+/*
+ * Driver for the SMSC LAN8710A
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+
+/* PHY special control/status register */
+#define SMSCPHY_SPCSR 0x1f
+#define SPCSR_SPDIND_10 0x0004
+#define SPCSR_SPDIND_100 0x0008
+#define SPCSR_SPDIND_SPDMASK 0x000c
+#define SPCSR_SPDIND_FDX 0x0010
+
+static int smscphy_match(device_t, cfdata_t, void *);
+static void smscphy_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(smscphy, sizeof (struct mii_softc),
+ smscphy_match, smscphy_attach, mii_phy_detach, mii_phy_activate);
+
+static void smscphy_power(struct mii_softc *, bool);
+static int smscphy_service(struct mii_softc *, struct mii_data *, int);
+static void smscphy_auto(struct mii_softc *, int);
+static void smscphy_status(struct mii_softc *);
+
+static const struct mii_phydesc smscphys[] = {
+ MII_PHY_DESC(SMSC, LAN8700),
+ MII_PHY_DESC(SMSC, LAN8710_LAN8720),
+ MII_PHY_END
+};
+
+static const struct mii_phy_funcs smscphy_funcs = {
+ smscphy_service,
+ smscphy_status,
+ mii_phy_reset
+};
+
+static int
+smscphy_match(device_t dev, cfdata_t match, void *aux)
+{
+ struct mii_attach_args *ma = aux;
+
+ if (mii_phy_match(ma, smscphys) != NULL)
+ return 10;
+
+ return 0;
+}
+
+static void
+smscphy_attach(device_t parent, device_t self, void *aux)
+{
+ struct mii_softc *sc = device_private(self);
+ struct mii_attach_args *ma = aux;
+ struct mii_data *mii = ma->mii_data;
+ const struct mii_phydesc *mpd;
+
+ mpd = mii_phy_match(ma, smscphys);
+ aprint_naive(": Media interface\n");
+ aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
+
+ sc->mii_dev = self;
+ sc->mii_inst = mii->mii_instance;
+ sc->mii_phy = ma->mii_phyno;
+ sc->mii_funcs = &smscphy_funcs;
+ sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
+ sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
+ sc->mii_mpd_rev = MII_REV(ma->mii_id2);
+ sc->mii_pdata = mii;
+ sc->mii_flags = ma->mii_flags;
+ sc->mii_anegticks = MII_ANEGTICKS;
+
+ PHY_RESET(sc);
+
+ PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
+ sc->mii_capabilities &= ma->mii_capmask;
+ aprint_normal_dev(self, "");
+ if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0)
+ aprint_error("no media present");
+ else
+ mii_phy_add_media(sc);
+ aprint_normal("\n");
+}
+
+static void
+smscphy_power(struct mii_softc *sc, bool power)
+{
+ uint16_t bmcr, new;
+
+ PHY_READ(sc, MII_BMCR, &bmcr);
+ if (power)
+ new = bmcr & ~BMCR_PDOWN;
+ else
+ new = bmcr | BMCR_PDOWN;
+ if (bmcr != new)
+ PHY_WRITE(sc, MII_BMCR, new);
+}
+
+static int
+smscphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
+ struct ifmedia_entry *ife;
+ uint16_t reg;
+
+ ife = mii->mii_media.ifm_cur;
+
+ switch (cmd) {
+ case MII_POLLSTAT:
+ break;
+
+ case MII_MEDIACHG:
+ /* Try to power up the PHY in case it's down */
+ if (IFM_SUBTYPE(ife->ifm_media) != IFM_NONE)
+ smscphy_power(sc, true);
+
+ switch (IFM_SUBTYPE(ife->ifm_media)) {
+ case IFM_AUTO:
+ smscphy_auto(sc, ife->ifm_media);
+ break;
+
+ default:
+ mii_phy_setmedia(sc);
+ if (IFM_SUBTYPE(ife->ifm_media) == IFM_NONE)
+ smscphy_power(sc, false);
+ break;
+ }
+ break;
+
+ case MII_TICK:
+ if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
+ break;
+
+ PHY_READ(sc, MII_BMSR, ®);
+ PHY_READ(sc, MII_BMSR, ®);
+ if (reg & BMSR_LINK) {
+ sc->mii_ticks = 0;
+ break;
+ }
+
+ if (++sc->mii_ticks <= MII_ANEGTICKS)
+ break;
+
+ PHY_RESET(sc);
+ smscphy_auto(sc, ife->ifm_media);
+ break;
+ }
+
+ /* Update the media status. */
+ PHY_STATUS(sc);
+
+ /* Callback if something changed. */
+ mii_phy_update(sc, cmd);
+ return 0;
+}
+
+static void
+smscphy_auto(struct mii_softc *sc, int media)
+{
+ uint16_t anar;
+
+ sc->mii_ticks = 0;
+ anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
+ if ((media & IFM_FLOW) != 0)
+ anar |= ANAR_FC;
+ PHY_WRITE(sc, MII_ANAR, anar);
+ /* Apparently this helps. */
+ PHY_READ(sc, MII_ANAR, &anar);
+ PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
+}
+
+static void
+smscphy_status(struct mii_softc *sc)
+{
+ struct mii_data *mii = sc->mii_pdata;
+ uint16_t bmcr, bmsr, status;
+
+ mii->mii_media_status = IFM_AVALID;
+ mii->mii_media_active = IFM_ETHER;
+
+ PHY_READ(sc, MII_BMSR, &bmsr);
+ PHY_READ(sc, MII_BMSR, &bmsr);
+ if ((bmsr & BMSR_LINK) != 0)
+ mii->mii_media_status |= IFM_ACTIVE;
+
+ PHY_READ(sc, MII_BMCR, &bmcr);
+ if ((bmcr & BMCR_ISO) != 0) {
+ mii->mii_media_active |= IFM_NONE;
+ mii->mii_media_status = 0;
+ return;
+ }
+
+ if ((bmcr & BMCR_LOOP) != 0)
+ mii->mii_media_active |= IFM_LOOP;
+
+ if ((bmcr & BMCR_AUTOEN) != 0) {
+ if ((bmsr & BMSR_ACOMP) == 0) {
+ /* Erg, still trying, I guess... */
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ }
+ }
+
+ PHY_READ(sc, SMSCPHY_SPCSR, &status);
+ if ((status & SPCSR_SPDIND_SPDMASK) == SPCSR_SPDIND_100)
+ mii->mii_media_active |= IFM_100_TX;
+ else
+ mii->mii_media_active |= IFM_10_T;
+ if (status & SPCSR_SPDIND_FDX)
+ mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
+ else
+ mii->mii_media_active |= IFM_HDX;
+}
