Module Name: src
Committed By: martin
Date: Mon Nov 25 16:18:41 UTC 2019
Modified Files:
src/sys/arch/arm/dts [netbsd-9]: sun50i-a64-pinebook.dts
src/sys/arch/arm/sunxi [netbsd-9]: sun50i_a64_ccu.c sunxi_ccu.h
sunxi_ccu_fractional.c sunxi_dwhdmi.c sunxi_hdmiphy.c
sunxi_hdmiphy.h sunxi_lcdc.c sunxi_mixer.c sunxi_platform.c
src/sys/dev/fdt [netbsd-9]: fdt_port.c
src/sys/dev/ic [netbsd-9]: dw_hdmi.c dw_hdmi.h
Log Message:
Pull up following revision(s) (requested by jmcneill in ticket #470):
sys/arch/arm/sunxi/sunxi_hdmiphy.c: revision 1.4
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.16
sys/dev/ic/dw_hdmi.c: revision 1.5
sys/arch/arm/sunxi/sunxi_hdmiphy.h: revision 1.2
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.17
sys/dev/ic/dw_hdmi.c: revision 1.6
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.18
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.19
sys/dev/ic/dw_hdmi.h: revision 1.5
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.8
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.9
sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.22
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.5
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.6
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.7
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.8
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.20
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.10
sys/arch/arm/dts/sun50i-a64-pinebook.dts: revision 1.17
sys/arch/arm/sunxi/sunxi_platform.c: revision 1.38
sys/dev/fdt/fdt_port.c: revision 1.3
sys/dev/fdt/fdt_port.c: revision 1.4
sys/arch/arm/sunxi/sunxi_ccu_fractional.c: revision 1.5
sys/arch/arm/sunxi/sunxi_lcdc.c: revision 1.7
sys/arch/arm/sunxi/sunxi_ccu_fractional.c: revision 1.6
sys/arch/arm/sunxi/sunxi_hdmiphy.c: revision 1.3
Fix CLK_BUS_HDMI bit
Enable TMDS clock
Store the flags passed to SUNXI_CCU_FRACTIONAL macro.
Previously the macro dropped the flags argument entirely, and did not
initialize the structure with it.
Allow bus glue to setup DDC clocks
Add TCON0 clock
HDMI PHY and TX share the same clocks. Do not enable clocks until both
reset resources have been deasserted. Explicitly set DDC clock dividers.
Honour SUNXI_CCU_FRACTIONAL_SET_ENABLE in fractional mode
Use fdtbus_get_reg to read "reg" property
Need to initialize the PHY before HPD sense and DDC will work
Set pixel clock on mode set
Set TCON1 parent to PLL_VIDEO1(1X)
Do not assume that an fb's pitch is width * 4 bytes.
Use actual hw mode, not proposed mode.
Set pre-divider M to 0 in fractional mode, as noted in user manual. Spotted by
jak.
Support non-zero fb start pixels.
Set video PLLs to 297MHz
Do not assume the cursor pitch is the same as the primary fb
Enable HDMI and HDMI audio
Try to avoid changing hardware settings when the "nomodeset" kernel arg
is present.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.16.2.1 src/sys/arch/arm/dts/sun50i-a64-pinebook.dts
cvs rdiff -u -r1.13.2.2 -r1.13.2.3 src/sys/arch/arm/sunxi/sun50i_a64_ccu.c
cvs rdiff -u -r1.21 -r1.21.4.1 src/sys/arch/arm/sunxi/sunxi_ccu.h
cvs rdiff -u -r1.4 -r1.4.4.1 src/sys/arch/arm/sunxi/sunxi_ccu_fractional.c
cvs rdiff -u -r1.3.6.1 -r1.3.6.2 src/sys/arch/arm/sunxi/sunxi_dwhdmi.c
cvs rdiff -u -r1.2 -r1.2.6.1 src/sys/arch/arm/sunxi/sunxi_hdmiphy.c
cvs rdiff -u -r1.1 -r1.1.6.1 src/sys/arch/arm/sunxi/sunxi_hdmiphy.h
cvs rdiff -u -r1.6 -r1.6.2.1 src/sys/arch/arm/sunxi/sunxi_lcdc.c
cvs rdiff -u -r1.7 -r1.7.6.1 src/sys/arch/arm/sunxi/sunxi_mixer.c
cvs rdiff -u -r1.37 -r1.37.2.1 src/sys/arch/arm/sunxi/sunxi_platform.c
cvs rdiff -u -r1.2 -r1.2.4.1 src/sys/dev/fdt/fdt_port.c
cvs rdiff -u -r1.1.6.1 -r1.1.6.2 src/sys/dev/ic/dw_hdmi.c \
src/sys/dev/ic/dw_hdmi.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
