Module Name: src
Committed By: martin
Date: Tue Nov 19 10:45:11 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-8]: specialreg.h
src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1450):
usr.sbin/cpuctl/arch/i386.c: revision 1.108
sys/arch/x86/include/specialreg.h: revision 1.158
Add the following bit definitions from the latest Intel SDM:
- CET shadow stack
- Fast Short REP MOV
- Hybrid part
- CET Indirect Branch Tracking
0x7d and 0x7e are for 10th generation Core (Ice Lake).
To generate a diff of this commit:
cvs rdiff -u -r1.98.2.16 -r1.98.2.17 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.74.6.7 -r1.74.6.8 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.98.2.16 src/sys/arch/x86/include/specialreg.h:1.98.2.17
--- src/sys/arch/x86/include/specialreg.h:1.98.2.16 Tue Nov 12 18:28:40 2019
+++ src/sys/arch/x86/include/specialreg.h Tue Nov 19 10:45:11 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.98.2.16 2019/11/12 18:28:40 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.98.2.17 2019/11/19 10:45:11 martin Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -400,6 +400,7 @@
#define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */
#define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */
#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */
+#define CPUID_SEF_CET_SS __BIT(7) /* CET shadow stack */
#define CPUID_SEF_GFNI __BIT(8)
#define CPUID_SEF_VAES __BIT(9)
#define CPUID_SEF_VPCLMULQDQ __BIT(10)
@@ -415,7 +416,7 @@
#define CPUID_SEF_FLAGS1 "\177\20" \
"b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
- "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" \
+ "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
"b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
"b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \
"f\21\5MAWAU\0" \
@@ -426,8 +427,11 @@
/* %edx */
#define CPUID_SEF_AVX512_4VNNIW __BIT(2)
#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
+#define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */
#define CPUID_SEF_MD_CLEAR __BIT(10)
#define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
+#define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */
+#define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */
#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
#define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */
@@ -437,8 +441,10 @@
#define CPUID_SEF_FLAGS2 "\20" \
"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
+ "\5" "FSREP_MOV" \
"\13" "MD_CLEAR" \
- "\16" "TSX_FORCE_ABORT" \
+ "\16" "TSX_FORCE_ABORT" "\20" "HYBRID" \
+ "\25" "CET_IBT" \
"\33" "IBRS" "\34" "STIBP" \
"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD"
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.74.6.7 src/usr.sbin/cpuctl/arch/i386.c:1.74.6.8
--- src/usr.sbin/cpuctl/arch/i386.c:1.74.6.7 Fri Aug 16 15:36:17 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Tue Nov 19 10:45:11 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.74.6.7 2019/08/16 15:36:17 martin Exp $ */
+/* $NetBSD: i386.c,v 1.74.6.8 2019/11/19 10:45:11 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74.6.7 2019/08/16 15:36:17 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.8 2019/11/19 10:45:11 martin Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -385,8 +385,8 @@ const struct cpu_cpuid_nameclass i386_cp
[0x6a] = "Future Xeon (Ice Lake)",
[0x6c] = "Future Xeon (Ice Lake)",
[0x7a] = "Atom (Goldmont Plus)",
- [0x7d] = "Future Core (Ice Lake)",
- [0x7e] = "Future Core (Ice Lake)",
+ [0x7d] = "10th gen Core (Ice Lake)",
+ [0x7e] = "10th gen Core (Ice Lake)",
[0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
[0x86] = "Atom (Tremont)",
[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
