Module Name: src
Committed By: jmcneill
Date: Sun Nov 10 11:43:04 UTC 2019
Modified Files:
src/sys/arch/arm/rockchip: rk3399_cru.c rk_cru.h rk_cru_composite.c
Log Message:
Force DCLK_VOP0/1 dividers to 1 and select closest match when setting PLL
rates.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/rockchip/rk3399_cru.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/rockchip/rk_cru.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rk_cru_composite.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
