Module Name: src
Committed By: jmcneill
Date: Mon Oct 14 11:00:13 UTC 2019
Modified Files:
src/sys/arch/arm/acpi: files.acpi gic_acpi.c gicv3_acpi.c
src/sys/arch/arm/cortex: files.cortex gic_v2m.c gic_v2m.h
Added Files:
src/sys/arch/arm/acpi: gic_v2m_acpi.c gic_v2m_acpi.h
Log Message:
Add support for Amazon's Graviton MSI controller.
Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/acpi/files.acpi
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/acpi/gic_acpi.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/acpi/gic_v2m_acpi.c \
src/sys/arch/arm/acpi/gic_v2m_acpi.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/acpi/gicv3_acpi.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/cortex/files.cortex
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gic_v2m.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/gic_v2m.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/acpi/files.acpi
diff -u src/sys/arch/arm/acpi/files.acpi:1.7 src/sys/arch/arm/acpi/files.acpi:1.8
--- src/sys/arch/arm/acpi/files.acpi:1.7 Sun Sep 22 18:31:59 2019
+++ src/sys/arch/arm/acpi/files.acpi Mon Oct 14 11:00:13 2019
@@ -1,4 +1,4 @@
-# $NetBSD: files.acpi,v 1.7 2019/09/22 18:31:59 jmcneill Exp $
+# $NetBSD: files.acpi,v 1.8 2019/10/14 11:00:13 jmcneill Exp $
#
# Configuration info for ACPI compliant ARM boards.
#
@@ -26,6 +26,8 @@ file arch/arm/acpi/gic_acpi.c gic_acpi
attach gicvthree at acpimadtbus with gicv3_acpi
file arch/arm/acpi/gicv3_acpi.c gicv3_acpi
+file arch/arm/acpi/gic_v2m_acpi.c (gic_acpi | gicv3_acpi) & pci
+
attach gtmr at acpisdtbus with gtmr_acpi
file arch/arm/acpi/gtmr_acpi.c gtmr_acpi
Index: src/sys/arch/arm/acpi/gic_acpi.c
diff -u src/sys/arch/arm/acpi/gic_acpi.c:1.3 src/sys/arch/arm/acpi/gic_acpi.c:1.4
--- src/sys/arch/arm/acpi/gic_acpi.c:1.3 Mon Nov 12 12:56:05 2018
+++ src/sys/arch/arm/acpi/gic_acpi.c Mon Oct 14 11:00:13 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_acpi.c,v 1.3 2018/11/12 12:56:05 jmcneill Exp $ */
+/* $NetBSD: gic_acpi.c,v 1.4 2019/10/14 11:00:13 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "pci.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic_acpi.c,v 1.3 2018/11/12 12:56:05 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_acpi.c,v 1.4 2019/10/14 11:00:13 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -43,16 +43,17 @@ __KERNEL_RCSID(0, "$NetBSD: gic_acpi.c,v
#include <dev/acpi/acpireg.h>
#include <dev/acpi/acpivar.h>
+#include <dev/fdt/fdtvar.h>
+
#include <arm/cortex/gic_intr.h>
#include <arm/cortex/gic_reg.h>
#include <arm/cortex/gic_v2m.h>
#include <arm/cortex/mpcore_var.h>
-#include <dev/fdt/fdtvar.h>
+#include <arm/acpi/gic_v2m_acpi.h>
#define GICD_SIZE 0x1000
#define GICC_SIZE 0x1000
-#define GICMSIFRAME_SIZE 0x1000
extern struct bus_space arm_generic_bs_tag;
extern struct pic_softc *pic_list[];
@@ -61,9 +62,6 @@ static int gic_acpi_match(device_t, cfda
static void gic_acpi_attach(device_t, device_t, void *);
static ACPI_STATUS gic_acpi_find_gicc(ACPI_SUBTABLE_HEADER *, void *);
-#if NPCI > 0
-static ACPI_STATUS gic_acpi_find_msi_frame(ACPI_SUBTABLE_HEADER *, void *);
-#endif
CFATTACH_DECL_NEW(gic_acpi, 0, gic_acpi_match, gic_acpi_attach, NULL, NULL);
@@ -130,7 +128,7 @@ gic_acpi_attach(device_t parent, device_
arm_fdt_irq_set_handler(armgic_irq_handler);
#if NPCI > 0
- acpi_madt_walk(gic_acpi_find_msi_frame, armgic);
+ acpi_madt_walk(gic_v2m_acpi_find_msi_frame, armgic);
#endif
}
@@ -146,46 +144,3 @@ gic_acpi_find_gicc(ACPI_SUBTABLE_HEADER
return AE_LIMIT;
}
-
-#if NPCI > 0
-static ACPI_STATUS
-gic_acpi_find_msi_frame(ACPI_SUBTABLE_HEADER *hdrp, void *aux)
-{
- ACPI_MADT_GENERIC_MSI_FRAME *msi_frame = (ACPI_MADT_GENERIC_MSI_FRAME *)hdrp;
- struct gic_v2m_frame *frame;
- struct pic_softc *pic = pic_list[0];
- device_t armgic = aux;
-
- if (hdrp->Type != ACPI_MADT_TYPE_GENERIC_MSI_FRAME)
- return AE_OK;
-
- frame = kmem_zalloc(sizeof(*frame), KM_SLEEP);
- frame->frame_reg = msi_frame->BaseAddress;
- frame->frame_pic = pic;
- if (msi_frame->Flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
- frame->frame_base = msi_frame->SpiBase;
- frame->frame_count = msi_frame->SpiCount;
- } else {
- bus_space_tag_t bst = &arm_generic_bs_tag;
- bus_space_handle_t bsh;
- if (bus_space_map(bst, frame->frame_reg, GICMSIFRAME_SIZE, 0, &bsh) != 0) {
- printf("%s: failed to map frame\n", __func__);
- return AE_OK;
- }
- const uint32_t typer = bus_space_read_4(bst, bsh, GIC_MSI_TYPER);
- bus_space_unmap(bst, bsh, GICMSIFRAME_SIZE);
-
- frame->frame_base = __SHIFTOUT(typer, GIC_MSI_TYPER_BASE);
- frame->frame_count = __SHIFTOUT(typer, GIC_MSI_TYPER_NUMBER);
- }
-
- if (gic_v2m_init(frame, armgic, msi_frame->MsiFrameId) != 0)
- aprint_error_dev(armgic, "failed to initialize GICv2m\n");
- else
- aprint_normal_dev(armgic, "GICv2m @ %#" PRIx64 ", SPIs %u-%u\n",
- (uint64_t)frame->frame_reg, frame->frame_base,
- frame->frame_base + frame->frame_count);
-
- return AE_OK;
-}
-#endif
Index: src/sys/arch/arm/acpi/gicv3_acpi.c
diff -u src/sys/arch/arm/acpi/gicv3_acpi.c:1.4 src/sys/arch/arm/acpi/gicv3_acpi.c:1.5
--- src/sys/arch/arm/acpi/gicv3_acpi.c:1.4 Thu Sep 12 09:02:36 2019
+++ src/sys/arch/arm/acpi/gicv3_acpi.c Mon Oct 14 11:00:13 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_acpi.c,v 1.4 2019/09/12 09:02:36 jmcneill Exp $ */
+/* $NetBSD: gicv3_acpi.c,v 1.5 2019/10/14 11:00:13 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3_acpi.c,v 1.4 2019/09/12 09:02:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_acpi.c,v 1.5 2019/10/14 11:00:13 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -52,6 +52,8 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3_acpi.c
#include <arm/cortex/gicv3_its.h>
#include <arm/cortex/gic_reg.h>
+#include <arm/acpi/gic_v2m_acpi.h>
+
#define GICD_SIZE 0x10000
#define GICR_SIZE 0x20000
#define GITS_SIZE 0x20000
@@ -71,7 +73,7 @@ static void gicv3_acpi_attach(device_t,
static int gicv3_acpi_map_dist(struct gicv3_acpi_softc *);
static int gicv3_acpi_map_redist(struct gicv3_acpi_softc *);
#if NPCI > 0
-static int gicv3_acpi_map_its(struct gicv3_acpi_softc *);
+static int gicv3_acpi_map_msi(struct gicv3_acpi_softc *);
#endif
CFATTACH_DECL_NEW(gicv3_acpi, sizeof(struct gicv3_acpi_softc), gicv3_acpi_match, gicv3_acpi_attach, NULL, NULL);
@@ -132,7 +134,7 @@ gicv3_acpi_attach(device_t parent, devic
}
#if NPCI > 0
- gicv3_acpi_map_its(sc);
+ gicv3_acpi_map_msi(sc);
#endif
arm_fdt_irq_set_handler(gicv3_irq_handler);
@@ -309,10 +311,12 @@ gicv3_acpi_map_gits(ACPI_SUBTABLE_HEADER
}
static int
-gicv3_acpi_map_its(struct gicv3_acpi_softc *sc)
+gicv3_acpi_map_msi(struct gicv3_acpi_softc *sc)
{
acpi_madt_walk(gicv3_acpi_map_gits, sc);
+ acpi_madt_walk(gic_v2m_acpi_find_msi_frame, sc->sc_gic.sc_dev);
return 0;
}
+
#endif
Index: src/sys/arch/arm/cortex/files.cortex
diff -u src/sys/arch/arm/cortex/files.cortex:1.12 src/sys/arch/arm/cortex/files.cortex:1.13
--- src/sys/arch/arm/cortex/files.cortex:1.12 Sat Aug 10 17:03:59 2019
+++ src/sys/arch/arm/cortex/files.cortex Mon Oct 14 11:00:13 2019
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.12 2019/08/10 17:03:59 skrll Exp $
+# $NetBSD: files.cortex,v 1.13 2019/10/14 11:00:13 jmcneill Exp $
defflag opt_cpu_in_cksum.h NEON_IN_CKSUM
@@ -15,13 +15,15 @@ file arch/arm/cortex/armperiph.c armper
device armgic: pic, pic_splfuncs
attach armgic at mpcorebus
file arch/arm/cortex/gic.c armgic
-file arch/arm/cortex/gic_v2m.c armgic & pci & __have_pci_msi_msix
# ARM Generic Interrupt Controller v3+
device gicvthree: pic, pic_splfuncs
file arch/arm/cortex/gicv3.c gicvthree
file arch/arm/cortex/gicv3_its.c gicvthree & pci & __have_pci_msi_msix
+# ARM GICv2m MSI support
+file arch/arm/cortex/gic_v2m.c (armgic | gicvthree) & pci & __have_pci_msi_msix
+
# ARM PL310 L2 Cache Controller(initially on Cortex-A9)
device arml2cc
attach arml2cc at mpcorebus
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.6 src/sys/arch/arm/cortex/gic_v2m.c:1.7
--- src/sys/arch/arm/cortex/gic_v2m.c:1.6 Mon Jun 17 00:49:55 2019
+++ src/sys/arch/arm/cortex/gic_v2m.c Mon Oct 14 11:00:13 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.7 2019/10/14 11:00:13 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.7 2019/10/14 11:00:13 jmcneill Exp $");
#include <sys/param.h>
#include <sys/kmem.h>
@@ -44,6 +44,24 @@ __KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v
#include <arm/pic/picvar.h>
#include <arm/cortex/gic_v2m.h>
+static uint64_t
+gic_v2m_msi_addr(struct gic_v2m_frame *frame, int spi)
+{
+ if ((frame->frame_flags & GIC_V2M_FLAG_GRAVITON) != 0)
+ return frame->frame_reg + ((spi - 32) << 3);
+
+ return frame->frame_reg + GIC_MSI_SETSPI;
+}
+
+static uint32_t
+gic_v2m_msi_data(struct gic_v2m_frame *frame, int spi)
+{
+ if ((frame->frame_flags & GIC_V2M_FLAG_GRAVITON) != 0)
+ return 0;
+
+ return spi;
+}
+
static int
gic_v2m_msi_alloc_spi(struct gic_v2m_frame *frame, int count,
const struct pci_attach_args *pa)
@@ -111,18 +129,20 @@ gic_v2m_msi_enable(struct gic_v2m_frame
ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
- const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI;
+ const uint64_t addr = gic_v2m_msi_addr(frame, spi);
+ const uint32_t data = gic_v2m_msi_data(frame, spi);
+
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO,
addr & 0xffffffff);
pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI,
(addr >> 32) & 0xffffffff);
- pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, spi);
+ pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, data);
} else {
pci_conf_write(pc, tag, off + PCI_MSI_MADDR,
addr & 0xffffffff);
- pci_conf_write(pc, tag, off + PCI_MSI_MDATA, spi);
+ pci_conf_write(pc, tag, off + PCI_MSI_MDATA, data);
}
ctl |= PCI_MSI_CTL_MSI_ENABLE;
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
@@ -162,11 +182,12 @@ gic_v2m_msix_enable(struct gic_v2m_frame
ctl &= ~PCI_MSIX_CTL_ENABLE;
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
- const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI;
+ const uint64_t addr = gic_v2m_msi_addr(frame, spi);
+ const uint32_t data = gic_v2m_msi_data(frame, spi);
const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32));
- bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, spi);
+ bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data);
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0);
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
Index: src/sys/arch/arm/cortex/gic_v2m.h
diff -u src/sys/arch/arm/cortex/gic_v2m.h:1.1 src/sys/arch/arm/cortex/gic_v2m.h:1.2
--- src/sys/arch/arm/cortex/gic_v2m.h:1.1 Sun Oct 21 00:42:05 2018
+++ src/sys/arch/arm/cortex/gic_v2m.h Mon Oct 14 11:00:13 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.h,v 1.1 2018/10/21 00:42:05 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.h,v 1.2 2019/10/14 11:00:13 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -40,6 +40,8 @@ struct gic_v2m_frame {
struct pic_softc *frame_pic;
uint16_t frame_base;
uint16_t frame_count;
+ uint32_t frame_flags;
+#define GIC_V2M_FLAG_GRAVITON 0x01 /* Amazon Graviton quirk */
const struct pci_attach_args *frame_pa[GICC_IAR_IRQ];
Added files:
Index: src/sys/arch/arm/acpi/gic_v2m_acpi.c
diff -u /dev/null src/sys/arch/arm/acpi/gic_v2m_acpi.c:1.1
--- /dev/null Mon Oct 14 11:00:13 2019
+++ src/sys/arch/arm/acpi/gic_v2m_acpi.c Mon Oct 14 11:00:13 2019
@@ -0,0 +1,122 @@
+/* $NetBSD: gic_v2m_acpi.c,v 1.1 2019/10/14 11:00:13 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jared McNeill <jmcne...@invisible.ca>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m_acpi.c,v 1.1 2019/10/14 11:00:13 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+#include <sys/kmem.h>
+
+#include <dev/acpi/acpireg.h>
+#include <dev/acpi/acpivar.h>
+
+#include <arm/cortex/gic_v2m.h>
+
+#include <arm/acpi/gic_v2m_acpi.h>
+
+#define GICMSIFRAME_SIZE 0x1000
+
+extern struct bus_space arm_generic_bs_tag;
+extern struct pic_softc *pic_list[];
+
+static const struct gic_v2m_acpi_quirk {
+ const char q_oemid[ACPI_OEM_ID_SIZE+1];
+ const char q_oemtableid[ACPI_OEM_TABLE_ID_SIZE+1];
+ uint32_t q_flags;
+} gic_v2m_acpi_quirks[] = {
+ { "AMAZON", "GRAVITON", GIC_V2M_FLAG_GRAVITON },
+};
+
+static uint32_t
+gic_v2m_acpi_flags(void)
+{
+ ACPI_TABLE_MADT *madt;
+ ACPI_STATUS rv;
+ int n;
+
+ rv = AcpiGetTable(ACPI_SIG_MADT, 0, (ACPI_TABLE_HEADER **)&madt);
+ if (ACPI_FAILURE(rv))
+ return 0;
+
+ for (n = 0; n < __arraycount(gic_v2m_acpi_quirks); n++) {
+ const struct gic_v2m_acpi_quirk *q = &gic_v2m_acpi_quirks[n];
+ if (memcmp(q->q_oemid, madt->Header.OemId, ACPI_OEM_ID_SIZE) == 0 &&
+ memcmp(q->q_oemtableid, madt->Header.OemTableId, ACPI_OEM_TABLE_ID_SIZE) == 0)
+ return q->q_flags;
+ }
+
+ return 0;
+}
+
+ACPI_STATUS
+gic_v2m_acpi_find_msi_frame(ACPI_SUBTABLE_HEADER *hdrp, void *aux)
+{
+ ACPI_MADT_GENERIC_MSI_FRAME *msi_frame = (ACPI_MADT_GENERIC_MSI_FRAME *)hdrp;
+ struct gic_v2m_frame *frame;
+ struct pic_softc *pic = pic_list[0];
+ device_t dev = aux;
+
+ if (hdrp->Type != ACPI_MADT_TYPE_GENERIC_MSI_FRAME)
+ return AE_OK;
+
+ frame = kmem_zalloc(sizeof(*frame), KM_SLEEP);
+ frame->frame_reg = msi_frame->BaseAddress;
+ frame->frame_pic = pic;
+ frame->frame_flags = gic_v2m_acpi_flags();
+ if (msi_frame->Flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
+ frame->frame_base = msi_frame->SpiBase;
+ frame->frame_count = msi_frame->SpiCount;
+ } else {
+ bus_space_tag_t bst = &arm_generic_bs_tag;
+ bus_space_handle_t bsh;
+ if (bus_space_map(bst, frame->frame_reg, GICMSIFRAME_SIZE, 0, &bsh) != 0) {
+ printf("%s: failed to map frame\n", __func__);
+ return AE_OK;
+ }
+ const uint32_t typer = bus_space_read_4(bst, bsh, GIC_MSI_TYPER);
+ bus_space_unmap(bst, bsh, GICMSIFRAME_SIZE);
+
+ frame->frame_base = __SHIFTOUT(typer, GIC_MSI_TYPER_BASE);
+ frame->frame_count = __SHIFTOUT(typer, GIC_MSI_TYPER_NUMBER);
+ }
+
+ if (gic_v2m_init(frame, dev, msi_frame->MsiFrameId) != 0)
+ aprint_error_dev(dev, "failed to initialize GICv2m\n");
+ else
+ aprint_normal_dev(dev, "GICv2m @ %#" PRIx64 ", SPIs %u-%u\n",
+ (uint64_t)frame->frame_reg, frame->frame_base,
+ frame->frame_base + frame->frame_count);
+
+ return AE_OK;
+}
Index: src/sys/arch/arm/acpi/gic_v2m_acpi.h
diff -u /dev/null src/sys/arch/arm/acpi/gic_v2m_acpi.h:1.1
--- /dev/null Mon Oct 14 11:00:13 2019
+++ src/sys/arch/arm/acpi/gic_v2m_acpi.h Mon Oct 14 11:00:13 2019
@@ -0,0 +1,37 @@
+/* $NetBSD: gic_v2m_acpi.h,v 1.1 2019/10/14 11:00:13 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2019 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jared McNeill <jmcne...@invisible.ca>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_GIC_V2M_ACPI_H
+#define _ARM_GIC_V2M_ACPI_H
+
+ACPI_STATUS gic_v2m_acpi_find_msi_frame(ACPI_SUBTABLE_HEADER *, void *);
+
+#endif /* !_ARM_GIC_V2M_ACPI_H */
