Module Name: src
Committed By: tnn
Date: Sun Sep 15 15:16:30 UTC 2019
Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c
src/sys/arch/aarch64/include: armreg.h
Log Message:
report A72 errata #859971 workaround status during boot
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.20 src/sys/arch/aarch64/aarch64/cpu.c:1.21
--- src/sys/arch/aarch64/aarch64/cpu.c:1.20 Tue Jul 16 20:29:53 2019
+++ src/sys/arch/aarch64/aarch64/cpu.c Sun Sep 15 15:16:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.20 2019/07/16 20:29:53 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.21 2019/09/15 15:16:30 tnn Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.20 2019/07/16 20:29:53 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.21 2019/09/15 15:16:30 tnn Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@@ -432,6 +432,14 @@ cpu_identify2(device_t self, struct cpu_
}
aprint_normal("\n");
+
+ if ((id->ac_midr & CPU_PARTMASK) == (CPU_ID_CORTEXA72R0 & CPU_PARTMASK)
+ && __SHIFTOUT(id->ac_midr, CPU_ID_REVISION_MASK) <= 3) {
+ aprint_normal_dev(self, "A72 errata #859971 present"
+ ", workaround %s\n",
+ ISSET(reg_a72_cpuactlr_el1_read(), __BIT(32))
+ ? "enabled" : "NOT enabled (U-Boot update needed)");
+ }
}
/*
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.27 src/sys/arch/aarch64/include/armreg.h:1.28
--- src/sys/arch/aarch64/include/armreg.h:1.27 Wed Sep 11 18:19:35 2019
+++ src/sys/arch/aarch64/include/armreg.h Sun Sep 15 15:16:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.27 2019/09/11 18:19:35 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.28 2019/09/15 15:16:30 tnn Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -260,6 +260,7 @@ AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
#define ID_AA64MMFR0_EL1_PARANGE_16T 4
#define ID_AA64MMFR0_EL1_PARANGE_256T 5
+AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0)
AARCH64REG_READ_INLINE(id_aa64mmfr1_el1)
AARCH64REG_READ_INLINE(id_aa64mmfr2_el1)
AARCH64REG_READ_INLINE(id_aa64pfr0_el1)
