CVS commit: src/sys/arch/arm/sunxi

[Manuel Bouyer]

Module Name:    src
Committed By:   bouyer
Date:           Thu Sep  5 17:25:24 UTC 2019

Modified Files:
        src/sys/arch/arm/sunxi: sunxi_mmc.c

Log Message:
The mmc module clock needs to be doubled only for 8bits DDR mode on old
timing hardware.
This makes the lime2-eemc works in 4bits DDR52 mode.


To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/sunxi/sunxi_mmc.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/arm/sunxi/sunxi_mmc.c
diff -u src/sys/arch/arm/sunxi/sunxi_mmc.c:1.36 src/sys/arch/arm/sunxi/sunxi_mmc.c:1.37
--- src/sys/arch/arm/sunxi/sunxi_mmc.c:1.36	Sun Sep  1 15:02:17 2019
+++ src/sys/arch/arm/sunxi/sunxi_mmc.c	Thu Sep  5 17:25:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_mmc.c,v 1.36 2019/09/01 15:02:17 jmcneill Exp $ */
+/* $NetBSD: sunxi_mmc.c,v 1.37 2019/09/05 17:25:23 bouyer Exp $ */
 
 /*-
  * Copyright (c) 2014-2017 Jared McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
 #include "opt_sunximmc.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.36 2019/09/01 15:02:17 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.37 2019/09/05 17:25:23 bouyer Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -481,7 +481,7 @@ free:
 }
 
 static int
-sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr)
+sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr, bool dbl)
 {
 	const struct sunxi_mmc_delay *delays;
 	int error, timing = SUNXI_MMC_TIMING_400K;
@@ -507,7 +507,7 @@ sunxi_mmc_set_clock(struct sunxi_mmc_sof
 			return EINVAL;
 	}
 
-	error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr);
+	error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << dbl);
 	if (error != 0)
 		return error;
 
@@ -555,7 +555,7 @@ sunxi_mmc_attach_i(device_t self)
 
 	sunxi_mmc_host_reset(sc);
 	sunxi_mmc_bus_width(sc, 1);
-	sunxi_mmc_set_clock(sc, 400, false);
+	sunxi_mmc_set_clock(sc, 400, false, false);
 
 	if (sc->sc_pwrseq)
 		fdtbus_mmc_pwrseq_post_power_on(sc->sc_pwrseq);
@@ -817,6 +817,7 @@ sunxi_mmc_bus_clock(sdmmc_chipset_handle
 	struct sunxi_mmc_softc *sc = sch;
 	uint32_t clkcr, gctrl, ntsr;
 	const u_int flags = sc->sc_config->flags;
+	bool dbl = 0;
 
 	clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR);
 	if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) {
@@ -834,9 +835,15 @@ sunxi_mmc_bus_clock(sdmmc_chipset_handle
 	}
 
 	if (freq) {
+		/* For 8bits ddr in old timing modes, and all ddr in new
+		 * timing modes, the module clock has to be 2x the card clock.
+		 */
+		if (ddr && ((flags & SUNXI_MMC_FLAG_NEW_TIMINGS) ||
+		    sc->sc_mmc_width == 8))
+			dbl = 1;
 
 		clkcr &= ~SUNXI_MMC_CLKCR_DIV;
-		clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV);
+		clkcr |= __SHIFTIN(dbl, SUNXI_MMC_CLKCR_DIV);
 		MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr);
 
 		if (flags & SUNXI_MMC_FLAG_NEW_TIMINGS) {
@@ -858,7 +865,7 @@ sunxi_mmc_bus_clock(sdmmc_chipset_handle
 			gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE;
 		MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl);
 
-		if (sunxi_mmc_set_clock(sc, freq, ddr) != 0)
+		if (sunxi_mmc_set_clock(sc, freq, ddr, dbl) != 0)
 			return 1;
 
 		clkcr |= SUNXI_MMC_CLKCR_CARDCLKON;