Module Name: src
Committed By: martin
Date: Fri Aug 16 15:28:38 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-8]: cacheinfo.h
src/sys/arch/x86/x86 [netbsd-8]: identcpu.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1338):
sys/arch/x86/include/cacheinfo.h: revision 1.27
sys/arch/x86/x86/identcpu.c: revision 1.74
Handle more Vortex CPU's from Andrius V.
While here refactor the code to make it smaller.
-
It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.
-
- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.
XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?
To generate a diff of this commit:
cvs rdiff -u -r1.22.10.2 -r1.22.10.3 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.55.2.7 -r1.55.2.8 src/sys/arch/x86/x86/identcpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.22.10.2 src/sys/arch/x86/include/cacheinfo.h:1.22.10.3
--- src/sys/arch/x86/include/cacheinfo.h:1.22.10.2 Mon Apr 9 18:04:32 2018
+++ src/sys/arch/x86/include/cacheinfo.h Fri Aug 16 15:28:38 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.22.10.2 2018/04/09 18:04:32 martin Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.22.10.3 2019/08/16 15:28:38 martin Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -362,6 +362,7 @@ __CI_TBL(0, 0x02, 2, 0, 0, NULL), \
__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
+__CI_TBL(0, 0x09, 16, 0, 0, NULL), \
__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \
__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.55.2.7 src/sys/arch/x86/x86/identcpu.c:1.55.2.8
--- src/sys/arch/x86/x86/identcpu.c:1.55.2.7 Wed Jun 12 10:17:32 2019
+++ src/sys/arch/x86/x86/identcpu.c Fri Aug 16 15:28:38 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.55.2.7 2019/06/12 10:17:32 martin Exp $ */
+/* $NetBSD: identcpu.c,v 1.55.2.8 2019/08/16 15:28:38 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55.2.7 2019/06/12 10:17:32 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55.2.8 2019/08/16 15:28:38 martin Exp $");
#include "opt_xen.h"
@@ -707,24 +707,18 @@ cpu_probe_vortex86(struct cpu_info *ci)
outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE | 0x90);
reg = inl(PCI_MODE1_DATA_REG);
- switch(reg) {
- case 0x31504d44:
- strcpy(cpu_brand_string, "Vortex86SX");
- break;
- case 0x32504d44:
- strcpy(cpu_brand_string, "Vortex86DX");
- break;
- case 0x33504d44:
- strcpy(cpu_brand_string, "Vortex86MX");
- break;
- case 0x37504d44:
- strcpy(cpu_brand_string, "Vortex86EX");
- break;
- default:
- strcpy(cpu_brand_string, "Unknown Vortex86");
- break;
+ if ((reg & 0xf8ffffff) != 0x30504d44) {
+ reg = 0;
+ } else {
+ reg = (reg >> 24) & 7;
}
+ static const char *cpu_vortex86_flavor[] = {
+ "??", "SX", "DX", "MX", "DX2", "MX+", "DX3", "EX",
+ };
+ snprintf(cpu_brand_string, sizeof(cpu_brand_string), "Vortex86%s",
+ cpu_vortex86_flavor[reg]);
+
#undef PCI_MODE1_ENABLE
#undef PCI_MODE1_ADDRESS_REG
#undef PCI_MODE1_DATA_REG
