Module Name: src
Committed By: skrll
Date: Thu Aug 15 09:07:34 UTC 2019
Modified Files:
src/sys/arch/aarch64/include: pte.h
Log Message:
Indent the field value defines. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/pte.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.6 src/sys/arch/aarch64/include/pte.h:1.7
--- src/sys/arch/aarch64/include/pte.h:1.6 Tue Aug 13 08:27:42 2019
+++ src/sys/arch/aarch64/include/pte.h Thu Aug 15 09:07:34 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.6 2019/08/13 08:27:42 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.7 2019/08/15 09:07:34 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -44,17 +44,17 @@ typedef uint64_t pt_entry_t; /* L3(4k) t
*/
#define LX_TBL_NSTABLE __BIT(63) /* inherited next level */
#define LX_TBL_APTABLE __BITS(62,61) /* inherited next level */
-#define LX_TBL_APTABLE_NOEFFECT __SHIFTIN(0,LX_TBL_APTABLE)
-#define LX_TBL_APTABLE_EL0_NOACCESS __SHIFTIN(1,LX_TBL_APTABLE)
-#define LX_TBL_APTABLE_RO __SHIFTIN(2,LX_TBL_APTABLE)
-#define LX_TBL_APTABLE_RO_EL0_NOREAD __SHIFTIN(3,LX_TBL_APTABLE)
+#define LX_TBL_APTABLE_NOEFFECT __SHIFTIN(0,LX_TBL_APTABLE)
+#define LX_TBL_APTABLE_EL0_NOACCESS __SHIFTIN(1,LX_TBL_APTABLE)
+#define LX_TBL_APTABLE_RO __SHIFTIN(2,LX_TBL_APTABLE)
+#define LX_TBL_APTABLE_RO_EL0_NOREAD __SHIFTIN(3,LX_TBL_APTABLE)
#define LX_TBL_UXNTABLE __BIT(60) /* inherited next level */
#define LX_TBL_PXNTABLE __BIT(59) /* inherited next level */
#define LX_BLKPAG_OS __BITS(58, 55)
-# define LX_BLKPAG_OS_0 __SHIFTIN(1,LX_BLKPAG_OS)
-# define LX_BLKPAG_OS_1 __SHIFTIN(2,LX_BLKPAG_OS)
-# define LX_BLKPAG_OS_2 __SHIFTIN(4,LX_BLKPAG_OS)
-# define LX_BLKPAG_OS_3 __SHIFTIN(8,LX_BLKPAG_OS)
+#define LX_BLKPAG_OS_0 __SHIFTIN(1,LX_BLKPAG_OS)
+#define LX_BLKPAG_OS_1 __SHIFTIN(2,LX_BLKPAG_OS)
+#define LX_BLKPAG_OS_2 __SHIFTIN(4,LX_BLKPAG_OS)
+#define LX_BLKPAG_OS_3 __SHIFTIN(8,LX_BLKPAG_OS)
#define LX_BLKPAG_UXN __BIT(54) /* Unprivileged Execute Never */
#define LX_BLKPAG_PXN __BIT(53) /* Privileged Execute Never */
#define LX_BLKPAG_CONTIG __BIT(52) /* Hint of TLB cache */
@@ -64,12 +64,12 @@ typedef uint64_t pt_entry_t; /* L3(4k) t
#define LX_BLKPAG_NG __BIT(11) /* Not Global */
#define LX_BLKPAG_AF __BIT(10) /* Access Flag */
#define LX_BLKPAG_SH __BITS(9,8) /* Shareability */
-#define LX_BLKPAG_SH_NS __SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */
-#define LX_BLKPAG_SH_OS __SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */
-#define LX_BLKPAG_SH_IS __SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */
+#define LX_BLKPAG_SH_NS __SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */
+#define LX_BLKPAG_SH_OS __SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */
+#define LX_BLKPAG_SH_IS __SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */
#define LX_BLKPAG_AP __BIT(7)
-#define LX_BLKPAG_AP_RW __SHIFTIN(0,LX_BLKPAG_AP) /* RW */
-#define LX_BLKPAG_AP_RO __SHIFTIN(1,LX_BLKPAG_AP) /* RO */
+#define LX_BLKPAG_AP_RW __SHIFTIN(0,LX_BLKPAG_AP) /* RW */
+#define LX_BLKPAG_AP_RO __SHIFTIN(1,LX_BLKPAG_AP) /* RO */
#define LX_BLKPAG_APUSER __BIT(6)
#define LX_BLKPAG_NS __BIT(5)
#define LX_BLKPAG_ATTR_INDX __BITS(4,2) /* refer MAIR_EL1 attr<n> */
@@ -78,9 +78,9 @@ typedef uint64_t pt_entry_t; /* L3(4k) t
#define LX_BLKPAG_ATTR_INDX_2 __SHIFTIN(2,LX_BLKPAG_ATTR_INDX)
#define LX_BLKPAG_ATTR_INDX_3 __SHIFTIN(3,LX_BLKPAG_ATTR_INDX)
#define LX_TYPE __BIT(1)
-#define LX_TYPE_BLK __SHIFTIN(0, LX_TYPE)
-#define LX_TYPE_TBL __SHIFTIN(1, LX_TYPE)
-#define L3_TYPE_PAG __SHIFTIN(1, LX_TYPE)
+#define LX_TYPE_BLK __SHIFTIN(0, LX_TYPE)
+#define LX_TYPE_TBL __SHIFTIN(1, LX_TYPE)
+#define L3_TYPE_PAG __SHIFTIN(1, LX_TYPE)
#define LX_VALID __BIT(0)
#define L1_BLK_OA __BITS(47, 30) /* 1GB */
@@ -130,57 +130,57 @@ typedef uint64_t pt_entry_t; /* L3(4k) t
/* TCR_EL1 - Translation Control Register */
-#define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */
-#define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */
-#define TCR_AS64K __BIT(36) /* Use 64K ASIDs */
-#define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */
-#define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */
-#define TCR_IPS_64TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */
-#define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */
-#define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */
-#define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */
-#define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */
-#define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */
-#define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */
-#define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */
-#define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */
-#define TCR_SH1 __BITS(29,28)
-#define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1)
-#define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1)
-#define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1)
-#define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */
-#define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */
-#define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */
-#define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */
-#define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */
-#define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */
-#define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */
-#define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */
-#define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */
-#define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */
-#define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */
-#define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */
-#define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */
-#define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */
-#define TCR_TG0_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */
-#define TCR_TG0_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */
-#define TCR_TG0_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */
-#define TCR_SH0 __BITS(13,12)
-#define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0)
-#define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0)
-#define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0)
-#define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */
-#define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */
-#define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */
-#define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */
-#define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */
-#define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */
-#define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */
-#define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */
-#define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */
-#define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */
-#define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
-#define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */
+#define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */
+#define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */
+#define TCR_AS64K __BIT(36) /* Use 64K ASIDs */
+#define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */
+#define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */
+#define TCR_IPS_64TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */
+#define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */
+#define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */
+#define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */
+#define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */
+#define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */
+#define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */
+#define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */
+#define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */
+#define TCR_SH1 __BITS(29,28)
+#define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1)
+#define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1)
+#define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1)
+#define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */
+#define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */
+#define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */
+#define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */
+#define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */
+#define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */
+#define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */
+#define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */
+#define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */
+#define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */
+#define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */
+#define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */
+#define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */
+#define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */
+#define TCR_TG0_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */
+#define TCR_TG0_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */
+#define TCR_TG0_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */
+#define TCR_SH0 __BITS(13,12)
+#define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0)
+#define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0)
+#define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0)
+#define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */
+#define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */
+#define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */
+#define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */
+#define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */
+#define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */
+#define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */
+#define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */
+#define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */
+#define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */
+#define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
+#define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */
/* TTBR0_EL1, TTBR1_EL1 - Translation Table Base Register */
