Module Name: src
Committed By: maxv
Date: Sun Jun 16 07:42:52 UTC 2019
Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv files.riscv kern.ldscript
src/sys/arch/riscv/include: pmap.h pte.h sysreg.h
src/sys/arch/riscv/riscv: db_machdep.c genassym.cf locore.S
pmap_machdep.c trap.c
Log Message:
Misc changes in RISC-V.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/conf/Makefile.riscv
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/conf/files.riscv
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/conf/kern.ldscript
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/pmap.h \
src/sys/arch/riscv/include/pte.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/db_machdep.c \
src/sys/arch/riscv/riscv/trap.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/genassym.cf
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/riscv/locore.S
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/pmap_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/Makefile.riscv
diff -u src/sys/arch/riscv/conf/Makefile.riscv:1.4 src/sys/arch/riscv/conf/Makefile.riscv:1.5
--- src/sys/arch/riscv/conf/Makefile.riscv:1.4 Sat Jun 1 12:42:27 2019
+++ src/sys/arch/riscv/conf/Makefile.riscv Sun Jun 16 07:42:52 2019
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.riscv,v 1.4 2019/06/01 12:42:27 maxv Exp $
+# $NetBSD: Makefile.riscv,v 1.5 2019/06/16 07:42:52 maxv Exp $
# Makefile for NetBSD
#
@@ -69,8 +69,8 @@ locore.o: ${RISCV}/riscv/locore.S assym.
## (5) link settings
##
.if ${MACHINE_ARCH} == "riscv64" && ${LP64:Uyes} == "yes"
-TEXTADDR?= 0xFFFFFFC000000000
-.else
+TEXTADDR?= 0xFFFFFFC000000000
+.else
TEXTADDR?= 0xC0001000
.endif
KERNLDSCRIPT?= ${RISCV}/conf/kern.ldscript
Index: src/sys/arch/riscv/conf/files.riscv
diff -u src/sys/arch/riscv/conf/files.riscv:1.2 src/sys/arch/riscv/conf/files.riscv:1.3
--- src/sys/arch/riscv/conf/files.riscv:1.2 Sat Jun 1 12:42:27 2019
+++ src/sys/arch/riscv/conf/files.riscv Sun Jun 16 07:42:52 2019
@@ -1,4 +1,4 @@
-# $NetBSD: files.riscv,v 1.2 2019/06/01 12:42:27 maxv Exp $
+# $NetBSD: files.riscv,v 1.3 2019/06/16 07:42:52 maxv Exp $
#
maxpartitions 16
@@ -41,7 +41,6 @@ file dev/md_root.c memory_disk_hooks
file kern/subr_disk_mbr.c disk
file uvm/pmap/pmap.c
-file uvm/pmap/pmap_pvt.c
file uvm/pmap/pmap_segtab.c
file uvm/pmap/pmap_tlb.c
Index: src/sys/arch/riscv/conf/kern.ldscript
diff -u src/sys/arch/riscv/conf/kern.ldscript:1.5 src/sys/arch/riscv/conf/kern.ldscript:1.6
--- src/sys/arch/riscv/conf/kern.ldscript:1.5 Mon Aug 24 08:13:07 2015
+++ src/sys/arch/riscv/conf/kern.ldscript Sun Jun 16 07:42:52 2019
@@ -1,82 +1,63 @@
-/* Script for -n: mix text and data on same page */
-OUTPUT_FORMAT("elf64-littleriscv")
OUTPUT_ARCH(riscv)
-ENTRY(_start)
+ENTRY(start)
+
+__PAGE_SIZE = 0x1000 ;
+__LARGE_PAGE_SIZE = 0x200000 ;
+
SECTIONS
{
- /* Read-only sections, merged into text segment: */
- PROVIDE (__executable_start = SEGMENT_START("text-segment", 0xffffffff80000000)); . = SEGMENT_START("text-segment", 0xffffffff80000000) + SIZEOF_HEADERS;
- .text :
- {
- _ftext = . ;
- *(.text)
- *(.text.unlikely .text.*_unlikely)
- *(.text.exit .text.exit.*)
- *(.text.startup .text.startup.*)
- *(.text.hot .text.hot.*)
- *(.stub .text.* .gnu.linkonce.t.*)
- }
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
- .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
- .rodata1 : { *(.rodata1) }
- .sdata2 :
- {
- *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
- }
- .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
- .eh_frame_hdr : { *(.eh_frame_hdr) }
- .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
- /* These sections are generated by the Sun/Oracle C++ compiler. */
- .exception_ranges : ONLY_IF_RO { *(.exception_ranges
- .exception_ranges*) }
- /* Adjust the address for the data segment. We want to adjust up to
- the same address within the page on the next page up. */
- . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
- /* Exception handling */
- .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
- .exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) }
- . = DATA_SEGMENT_RELRO_END (0, .);
- .data :
- {
- _fdata = . ;
- *(.data .data.* .gnu.linkonce.d.*)
- SORT(CONSTRUCTORS)
- }
- .data1 : { *(.data1) }
- /* We want the small data sections together, so single-instruction offsets
- can access them all, and initialized data all before uninitialized, so
- we can shorten the on-disk segment size. */
- .sdata :
- {
- /*_gp = . + 0x800;*/
- *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- }
- _edata = .; PROVIDE (edata = .);
- . = .;
- __bss_start = .;
- _fbss = .;
- .sbss :
- {
- *(.dynsbss)
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon)
- }
- .bss :
- {
- *(.dynbss)
- *(.bss .bss.* .gnu.linkonce.b.*)
- *(COMMON)
- /* Align here to ensure that the .bss section occupies space up to
- _end. Align after .bss to ensure correct alignment even if the
- .bss section disappears because there are no input sections.
- FIXME: Why do we need it? When there is no .bss section, we don't
- pad the .data section. */
- . = ALIGN(. != 0 ? 64 / 8 : 1);
- }
- . = ALIGN(64 / 8);
- _end = .; PROVIDE (end = .);
- . = DATA_SEGMENT_END (.);
+ .text : AT (ADDR(.text) & 0x0fffffff)
+ {
+ *(.text)
+ *(.text.*)
+ *(.stub)
+ }
+ _etext = . ;
+ PROVIDE (etext = .);
+
+ . = ALIGN(__LARGE_PAGE_SIZE);
+
+ __rodata_start = . ;
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ *(.srodata)
+ *(.srodata.*)
+ }
+
+ . = ALIGN(__LARGE_PAGE_SIZE);
+
+ __data_start = . ;
+ .data :
+ {
+ *(.data)
+ *(.sdata)
+ *(.sdata.*)
+ }
+ _edata = . ;
+ PROVIDE (edata = .) ;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.sbss)
+ *(.sbss.*)
+ *(COMMON)
+ . = ALIGN(__LARGE_PAGE_SIZE);
+ }
+
+ . = ALIGN(__PAGE_SIZE);
+
+ /* End of the kernel image */
+ __kernel_end = . ;
+
+ _end = . ;
+ PROVIDE (end = .) ;
+ .note.netbsd.ident :
+ {
+ KEEP(*(.note.netbsd.ident));
+ }
}
Index: src/sys/arch/riscv/include/pmap.h
diff -u src/sys/arch/riscv/include/pmap.h:1.2 src/sys/arch/riscv/include/pmap.h:1.3
--- src/sys/arch/riscv/include/pmap.h:1.2 Sat Jun 1 12:42:28 2019
+++ src/sys/arch/riscv/include/pmap.h Sun Jun 16 07:42:52 2019
@@ -1,11 +1,11 @@
-/* $NetBSD: pmap.h,v 1.2 2019/06/01 12:42:28 maxv Exp $ */
+/* $NetBSD: pmap.h,v 1.3 2019/06/16 07:42:52 maxv Exp $ */
-/*-
- * Copyright (c) 2014 The NetBSD Foundation, Inc.
+/*
+ * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
- * by Matt Thomas of 3am Software Foundry.
+ * by Matt Thomas (of 3am Software Foundry) and Maxime Villard.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -47,17 +47,19 @@
#include <riscv/pte.h>
-#define PMAP_SEGTABSIZE NPTEPG
+#define PMAP_SEGTABSIZE NPTEPG
+
+#define NBSEG (PAGE_SIZE * NPTEPG)
-#define NBSEG (NBPG*NPTEPG)
#ifdef _LP64
-#define NBXSEG (NBSEG*NSEGPG)
+#define NBXSEG (NBSEG * NSEGPG)
#define XSEGSHIFT (SEGSHIFT + PGSHIFT - 3)
-#define XSEGOFSET (PTE_PPN1|SEGOFSET)
+#define XSEGOFSET (PTE_PPN1 | SEGOFSET)
#define SEGSHIFT (PGSHIFT + PGSHIFT - 3)
#else
#define SEGSHIFT (PGSHIFT + PGSHIFT - 2)
#endif
+
#define SEGOFSET (PTE_PPN0|PAGE_MASK)
#define KERNEL_PID 0
@@ -92,9 +94,7 @@ pmap_procwr(struct proc *p, vaddr_t va,
__asm __volatile("fence\trw,rw; fence.i");
}
-
#include <uvm/pmap/tlb.h>
-
#include <uvm/pmap/pmap_tlb.h>
#define PMAP_GROWKERNEL
@@ -124,6 +124,11 @@ void pmap_md_pdetab_activate(struct pmap
void pmap_md_pdetab_init(struct pmap *);
bool pmap_md_ok_to_steal_p(const uvm_physseg_t, size_t);
+extern vaddr_t pmap_direct_base;
+extern vaddr_t pmap_direct_end;
+#define PMAP_DIRECT_MAP(pa) (pmap_direct_base + (pa))
+#define PMAP_DIRECT_UNMAP(va) ((paddr_t)(va) - pmap_direct_base)
+
#ifdef __PMAP_PRIVATE
static inline void
pmap_md_page_syncicache(struct vm_page *pg, const kcpuset_t *kc)
@@ -159,9 +164,6 @@ pmap_md_tlb_asid_max(void)
#endif /* __PMAP_PRIVATE */
#endif /* _KERNEL */
-#define POOL_VTOPHYS(va) ((paddr_t)((vaddr_t)(va)-VM_MAX_KERNEL_ADDRESS))
-#define POOL_PHYSTOV(pa) ((vaddr_t)(paddr_t)(pa)+VM_MAX_KERNEL_ADDRESS)
-
#include <uvm/pmap/pmap.h>
#endif /* !_MODULE */
Index: src/sys/arch/riscv/include/pte.h
diff -u src/sys/arch/riscv/include/pte.h:1.2 src/sys/arch/riscv/include/pte.h:1.3
--- src/sys/arch/riscv/include/pte.h:1.2 Sat Jun 1 12:42:28 2019
+++ src/sys/arch/riscv/include/pte.h Sun Jun 16 07:42:52 2019
@@ -1,10 +1,11 @@
-/* $NetBSD: pte.h,v 1.2 2019/06/01 12:42:28 maxv Exp $ */
-/*-
- * Copyright (c) 2014 The NetBSD Foundation, Inc.
+/* $NetBSD: pte.h,v 1.3 2019/06/16 07:42:52 maxv Exp $ */
+
+/*
+ * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
- * by Matt Thomas of 3am Software Foundry.
+ * by Matt Thomas (of 3am Software Foundry) and Maxime Villard.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -31,68 +32,63 @@
#ifndef _RISCV_PTE_H_
#define _RISCV_PTE_H_
-//
-// RV32 page table entry (4 GB VA space)
-// [31..22] = PPN[1]
-// [21..12] = PPN[0]
-// [11.. 9] = software
-//
-// RV64 page table entry (4 TB VA space)
-// [64..43] = 0
-// [42..33] = PPN[2]
-// [32..23] = PPN[1]
-// [22..13] = PPN[0]
-// [12.. 9] = software
-//
-// Common to both:
-// [8] = SX
-// [7] = SW
-// [6] = SR
-// [5] = UX
-// [4] = UW
-// [3] = UR
-// [2] = G
-// [1] = T
-// [0] = V
-//
-
-#define NPTEPG (1 + __BITS(9, 0)) // PTEs per Page
-#define NSEGPG NPTEPG
-#define NPDEPG NPTEPG
-#ifdef _LP64
-#define PTE_PPN __BITS(63, 13) // Physical Page Number
-#define PTE_PPN0 __BITS(42, 33) // 1K 8-byte SDEs / PAGE
-#define PTE_PPN1 __BITS(32, 23) // 1K 8-byte PDEs / PAGE
-#define PTE_PPN2 __BITS(22, 13) // 1K 8-byte PTEs / PAGE
+#ifdef _LP64 /* Sv39 */
+#define PTE_PPN __BITS(53, 10)
+#define PTE_PPN0 __BITS(18, 10)
+#define PTE_PPN1 __BITS(27, 19)
+#define PTE_PPN2 __BITS(53, 28)
typedef __uint64_t pt_entry_t;
typedef __uint64_t pd_entry_t;
#define atomic_cas_pte atomic_cas_64
-#define atomic_cas_pde atomic_cas_64
-#else
-#define PTE_PPN __BITS(31, 12) // Physical Page Number
-#define PTE_PPN0 __BITS(31, 22) // 1K 4-byte PDEs / PAGE
-#define PTE_PPN1 __BITS(21, 12) // 1K 4-byte PTEs / PAGE
+#else /* Sv32 */
+#define PTE_PPN __BITS(31, 10)
+#define PTE_PPN0 __BITS(19, 10)
+#define PTE_PPN1 __BITS(31, 20)
typedef __uint32_t pt_entry_t;
typedef __uint32_t pd_entry_t;
#define atomic_cas_pte atomic_cas_32
-#define atomic_cas_pde atomic_cas_32
#endif
-// These only mean something to NetBSD
-#define PTE_NX __BIT(11) // Unexecuted
-#define PTE_NW __BIT(10) // Unmodified
-#define PTE_WIRED __BIT(9) // Do Not Delete
-
-// These are hardware defined bits
-#define PTE_SX __BIT(8) // Supervisor eXecute
-#define PTE_SW __BIT(7) // Supervisor Write
-#define PTE_SR __BIT(6) // Supervisor Read
-#define PTE_UX __BIT(5) // User eXecute
-#define PTE_UW __BIT(4) // User Write
-#define PTE_UR __BIT(3) // User Read
-#define PTE_G __BIT(2) // Global
-#define PTE_T __BIT(1) // "Transit" (non-leaf)
-#define PTE_V __BIT(0) // Valid
+#define PTE_PPN_SHIFT 10
+
+#define NPTEPG (PAGE_SIZE / sizeof(pt_entry_t))
+#define NSEGPG NPTEPG
+#define NPDEPG NPTEPG
+
+/* Software PTE bits. */
+#define PTE_WIRED __BIT(8)
+
+/* Hardware PTE bits. */
+#define PTE_D __BIT(7)
+#define PTE_A __BIT(6)
+#define PTE_G __BIT(5)
+#define PTE_U __BIT(4)
+#define PTE_X __BIT(3)
+#define PTE_W __BIT(2)
+#define PTE_R __BIT(1)
+#define PTE_V __BIT(0)
+
+#define PA_TO_PTE(pa) (((pa) >> PAGE_SHIFT) << PTE_PPN_SHIFT)
+#define PTE_TO_PA(pte) (((pte) >> PTE_PPN_SHIFT) << PAGE_SHIFT)
+
+#define L2_SHIFT 30
+#define L1_SHIFT 21
+#define L0_SHIFT 12
+
+#define L2_SIZE (1 << L2_SHIFT)
+#define L1_SIZE (1 << L1_SHIFT)
+#define L0_SIZE (1 << L0_SHIFT)
+
+#define L2_OFFSET (L2_SIZE - 1)
+#define L1_OFFSET (L1_SIZE - 1)
+#define L0_OFFSET (L0_SIZE - 1)
+
+#define Ln_ENTRIES (1 << 9)
+#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
+
+#define pl2_i(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
+#define pl1_i(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
+#define pl0_i(va) (((va) >> L0_SHIFT) & Ln_ADDR_MASK)
static inline bool
pte_valid_p(pt_entry_t pte)
@@ -109,7 +105,7 @@ pte_wired_p(pt_entry_t pte)
static inline bool
pte_modified_p(pt_entry_t pte)
{
- return (pte & PTE_NW) == 0 && (pte & (PTE_UW|PTE_SW)) != 0;
+ return (pte & PTE_D) != 0;
}
static inline bool
@@ -121,7 +117,7 @@ pte_cached_p(pt_entry_t pte)
static inline bool
pte_deferred_exec_p(pt_entry_t pte)
{
- return (pte & PTE_NX) != 0;
+ return false;
}
static inline pt_entry_t
@@ -151,36 +147,37 @@ pte_nv_entry(bool kernel_p)
static inline pt_entry_t
pte_prot_nowrite(pt_entry_t pte)
{
- return pte & ~(PTE_NW|PTE_SW|PTE_UW);
+ return pte & ~PTE_W;
}
static inline pt_entry_t
pte_prot_downgrade(pt_entry_t pte, vm_prot_t newprot)
{
- pte &= ~(PTE_NW|PTE_SW|PTE_UW);
+ if ((newprot & VM_PROT_READ) == 0)
+ pte &= ~PTE_R;
+ if ((newprot & VM_PROT_WRITE) == 0)
+ pte &= ~PTE_W;
if ((newprot & VM_PROT_EXECUTE) == 0)
- pte &= ~(PTE_NX|PTE_SX|PTE_UX);
+ pte &= ~PTE_X;
return pte;
}
static inline pt_entry_t
pte_prot_bits(struct vm_page_md *mdpg, vm_prot_t prot, bool kernel_p)
{
+ pt_entry_t pte;
+
KASSERT(prot & VM_PROT_READ);
- pt_entry_t pt_entry = PTE_SR | (kernel_p ? 0 : PTE_UR);
+
+ pte = PTE_R;
if (prot & VM_PROT_EXECUTE) {
- if (mdpg != NULL && !VM_PAGEMD_EXECPAGE_P(mdpg))
- pt_entry |= PTE_NX;
- else
- pt_entry |= kernel_p ? PTE_SX : PTE_UX;
+ pte |= PTE_X;
}
if (prot & VM_PROT_WRITE) {
- if (mdpg != NULL && !VM_PAGEMD_MODIFIED_P(mdpg))
- pt_entry |= PTE_NW;
- else
- pt_entry |= PTE_SW | (kernel_p ? 0 : PTE_UW);
+ pte |= PTE_W;
}
- return pt_entry;
+
+ return pte;
}
static inline pt_entry_t
@@ -207,9 +204,9 @@ pte_flag_bits(struct vm_page_md *mdpg, i
static inline pt_entry_t
pte_make_enter(paddr_t pa, struct vm_page_md *mdpg, vm_prot_t prot,
- int flags, bool kernel_p)
+ int flags, bool kernel_p)
{
- pt_entry_t pte = (pt_entry_t) pa & ~PAGE_MASK;
+ pt_entry_t pte = (pt_entry_t)PA_TO_PTE(pa);
pte |= pte_flag_bits(mdpg, flags, kernel_p);
pte |= pte_prot_bits(mdpg, prot, kernel_p);
@@ -222,9 +219,9 @@ pte_make_enter(paddr_t pa, struct vm_pag
static inline pt_entry_t
pte_make_kenter_pa(paddr_t pa, struct vm_page_md *mdpg, vm_prot_t prot,
- int flags)
+ int flags)
{
- pt_entry_t pte = (pt_entry_t) pa & ~PAGE_MASK;
+ pt_entry_t pte = (pt_entry_t)PA_TO_PTE(pa);
pte |= PTE_WIRED | PTE_V;
pte |= pte_flag_bits(NULL, flags, true);
@@ -239,27 +236,6 @@ pte_set(pt_entry_t *ptep, pt_entry_t pte
*ptep = pte;
}
-static inline paddr_t
-pte_pde_to_paddr(pd_entry_t pde)
-{
- return pde & ~PAGE_MASK;
-}
-
-static inline pd_entry_t
-pte_pde_cas(pd_entry_t *pdep, pd_entry_t opde, pt_entry_t npde)
-{
-#ifdef MULTIPROCESSOR
-#ifdef _LP64
- return atomic_cas_64(pdep, opde, npde);
-#else
- return atomic_cas_32(pdep, opde, npde);
-#endif
-#else
- *pdep = npde;
- return 0;
-#endif
-}
-
static inline pt_entry_t
pte_value(pt_entry_t pte)
{
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.3 src/sys/arch/riscv/include/sysreg.h:1.4
--- src/sys/arch/riscv/include/sysreg.h:1.3 Tue Mar 31 01:14:02 2015
+++ src/sys/arch/riscv/include/sysreg.h Sun Jun 16 07:42:52 2019
@@ -1,5 +1,6 @@
-/* $NetBSD: sysreg.h,v 1.3 2015/03/31 01:14:02 matt Exp $ */
-/*-
+/* $NetBSD: sysreg.h,v 1.4 2019/06/16 07:42:52 maxv Exp $ */
+
+/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
*
@@ -189,32 +190,32 @@ riscvreg_cycle_read(void)
#endif
}
-static inline uintptr_t
-riscvreg_ptbr_read(void)
-{
- uintptr_t __ptbr;
- __asm("csrr\t%0, sptbr" : "=r"(__ptbr));
- return __ptbr;
-}
-
-static inline void
-riscvreg_ptbr_write(uint32_t __ptbr)
-{
- __asm("csrw\tsptbr, %0" :: "r"(__ptbr));
-}
+#ifdef _LP64
+#define SATP_MODE __BITS(63,60)
+#define SATP_ASID __BITS(59,44)
+#define SATP_PPN __BITS(43,0)
+#else
+#define SATP_MODE __BIT(31)
+#define SATP_ASID __BITS(30,22)
+#define SATP_PPN __BITS(21,0)
+#endif
static inline uint32_t
riscvreg_asid_read(void)
{
- uint32_t __asid;
- __asm __volatile("csrr\t%0, sasid" : "=r"(__asid));
- return __asid;
+ uintptr_t satp;
+ __asm __volatile("csrr %0, satp" : "=r" (satp));
+ return __SHIFTOUT(satp, SATP_ASID);
}
static inline void
-riscvreg_asid_write(uint32_t __asid)
+riscvreg_asid_write(uint32_t asid)
{
- __asm __volatile("csrw\tsasid, %0" :: "r"(__asid));
+ uintptr_t satp;
+ __asm __volatile("csrr %0, satp" : "=r" (satp));
+ satp &= ~SATP_ASID;
+ satp |= __SHIFTIN((uintptr_t)asid, SATP_ASID);
+ __asm __volatile("csrw satp, %0" :: "r" (satp));
}
#endif /* _RISCV_SYSREG_H_ */
Index: src/sys/arch/riscv/riscv/db_machdep.c
diff -u src/sys/arch/riscv/riscv/db_machdep.c:1.2 src/sys/arch/riscv/riscv/db_machdep.c:1.3
--- src/sys/arch/riscv/riscv/db_machdep.c:1.2 Mon Apr 23 15:40:33 2018
+++ src/sys/arch/riscv/riscv/db_machdep.c Sun Jun 16 07:42:52 2019
@@ -29,7 +29,7 @@
#include <sys/cdefs.h>
-__RCSID("$NetBSD: db_machdep.c,v 1.2 2018/04/23 15:40:33 christos Exp $");
+__RCSID("$NetBSD: db_machdep.c,v 1.3 2019/06/16 07:42:52 maxv Exp $");
#include <sys/param.h>
@@ -41,6 +41,8 @@ __RCSID("$NetBSD: db_machdep.c,v 1.2 201
#include <ddb/db_extern.h>
#include <ddb/db_variables.h>
+int db_active = 0;
+
static int db_rw_ddbreg(const struct db_variable *, db_expr_t *, int);
const struct db_variable db_regs[] = {
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.2 src/sys/arch/riscv/riscv/trap.c:1.3
--- src/sys/arch/riscv/riscv/trap.c:1.2 Sat Apr 6 03:06:27 2019
+++ src/sys/arch/riscv/riscv/trap.c Sun Jun 16 07:42:52 2019
@@ -30,8 +30,9 @@
#include <sys/cdefs.h>
#define __PMAP_PRIVATE
+#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.2 2019/04/06 03:06:27 thorpej Exp $");
+__RCSID("$NetBSD: trap.c,v 1.3 2019/06/16 07:42:52 maxv Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -247,7 +248,7 @@ static bool
trap_pagefault_fixup(struct trapframe *tf, struct pmap *pmap, register_t cause,
intptr_t addr)
{
- pt_entry_t * const ptep = pmap_pte_lookup(pmap, addr, NULL);
+ pt_entry_t * const ptep = pmap_pte_lookup(pmap, addr);
struct vm_page *pg;
if (ptep == NULL)
@@ -270,6 +271,7 @@ trap_pagefault_fixup(struct trapframe *t
npte |= PTE_V;
attr |= VM_PAGEMD_REFERENCED;
}
+#if 0 /* XXX Outdated */
if (cause == CAUSE_FAULT_STORE) {
if ((npte & PTE_NW) != 0) {
npte &= ~PTE_NW;
@@ -281,7 +283,7 @@ trap_pagefault_fixup(struct trapframe *t
attr |= VM_PAGEMD_EXECPAGE;
}
}
-
+#endif
if (attr == 0)
return false;
Index: src/sys/arch/riscv/riscv/genassym.cf
diff -u src/sys/arch/riscv/riscv/genassym.cf:1.4 src/sys/arch/riscv/riscv/genassym.cf:1.5
--- src/sys/arch/riscv/riscv/genassym.cf:1.4 Sat Jun 1 12:42:28 2019
+++ src/sys/arch/riscv/riscv/genassym.cf Sun Jun 16 07:42:52 2019
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.4 2019/06/01 12:42:28 maxv Exp $
+# $NetBSD: genassym.cf,v 1.5 2019/06/16 07:42:52 maxv Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
# All rights reserved.
@@ -187,12 +187,14 @@ define PGSHIFT PGSHIFT
define NPDEPG NPDEPG
define NBSEG NBSEG
-define PTE_T PTE_T
-define PTE_V PTE_V
+define PTE_D PTE_D
+define PTE_A PTE_A
define PTE_G PTE_G
-define PTE_SX PTE_SX
-define PTE_SW PTE_SW
-define PTE_SR PTE_SR
+define PTE_U PTE_U
+define PTE_X PTE_X
+define PTE_W PTE_W
+define PTE_R PTE_R
+define PTE_V PTE_V
define PM_MD_PDETAB offsetof(struct pmap, pm_md.md_pdetab)
define PM_MD_PTBR offsetof(struct pmap, pm_md.md_ptbr)
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.8 src/sys/arch/riscv/riscv/locore.S:1.9
--- src/sys/arch/riscv/riscv/locore.S:1.8 Sat Jun 1 12:42:28 2019
+++ src/sys/arch/riscv/riscv/locore.S Sun Jun 16 07:42:52 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.8 2019/06/01 12:42:28 maxv Exp $ */
+/* $NetBSD: locore.S,v 1.9 2019/06/16 07:42:52 maxv Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -51,6 +51,11 @@ ENTRY_NP(start)
li s10, PAGE_SIZE
li s9, USPACE
+ /*
+ * XXX XXX XXX: This is completely broken and wrong, we should map only
+ * the kernel sections, and the direct map should be mapped later in C.
+ */
+#if 0
#if 0
// The kernel doesn't use gp/_gp since we'd have to reload it on
// each exception.
@@ -91,11 +96,7 @@ ENTRY_NP(start)
REG_S t0, -SZREG(s3) // store in highest first level PDE
#endif
- /*
- * XXX XXX XXX: This is completely broken and wrong, we should map only
- * the kernel sections, and the direct map should be mapped later in C.
- */
-#if 0 && (VM_MIN_KERNEL_ADDRESS >> XSEGSHIFT) != (VM_MAX_KERNEL_ADDRESS >> XSEGSHIFT)
+#if (VM_MIN_KERNEL_ADDRESS >> XSEGSHIFT) != (VM_MAX_KERNEL_ADDRESS >> XSEGSHIFT)
#error VM_MIN_KERNEL_ADDRESS not in same first level PDE as VM_MAX_KERNEL_ADDRESS
#endif
// We allocated the kernel first PTE page so let's insert in the
@@ -124,6 +125,7 @@ ENTRY_NP(start)
add s3, s3, SZREG // advance to next PDE slot
addi a7, a7, -1 // count down segment
bgtz a6, .Lfill // loop if more
+#endif
csrw sptbr, s1 // set the page table base
li t0, SR_VM
Index: src/sys/arch/riscv/riscv/pmap_machdep.c
diff -u src/sys/arch/riscv/riscv/pmap_machdep.c:1.3 src/sys/arch/riscv/riscv/pmap_machdep.c:1.4
--- src/sys/arch/riscv/riscv/pmap_machdep.c:1.3 Sat Jun 1 12:42:28 2019
+++ src/sys/arch/riscv/riscv/pmap_machdep.c Sun Jun 16 07:42:52 2019
@@ -1,9 +1,11 @@
-/*-
- * Copyright (c) 2014 The NetBSD Foundation, Inc.
+/* $NetBSD: pmap_machdep.c,v 1.4 2019/06/16 07:42:52 maxv Exp $ */
+
+/*
+ * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
- * by Matt Thomas of 3am Software Foundry.
+ * by Matt Thomas (of 3am Software Foundry) and Maxime Villard.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -31,7 +33,7 @@
#include <sys/cdefs.h>
-__RCSID("$NetBSD: pmap_machdep.c,v 1.3 2019/06/01 12:42:28 maxv Exp $");
+__RCSID("$NetBSD: pmap_machdep.c,v 1.4 2019/06/16 07:42:52 maxv Exp $");
#include <sys/param.h>
@@ -41,24 +43,27 @@ __RCSID("$NetBSD: pmap_machdep.c,v 1.3 2
int riscv_poolpage_vmfreelist = VM_FREELIST_DEFAULT;
+vaddr_t pmap_direct_base __read_mostly;
+vaddr_t pmap_direct_end __read_mostly;
+
void
pmap_zero_page(paddr_t pa)
{
-#ifdef POOL_PHYSTOV
- memset((void *)POOL_PHYSTOV(pa), 0, PAGE_SIZE);
+#ifdef PMAP_DIRECT_MAP
+ memset((void *)PMAP_DIRECT_MAP(pa), 0, PAGE_SIZE);
#else
-#error FIX pmap_zero_page!
+#error "no direct map"
#endif
}
void
pmap_copy_page(paddr_t src, paddr_t dst)
{
-#ifdef POOL_PHYSTOV
- memcpy((void *)POOL_PHYSTOV(dst), (const void *)POOL_PHYSTOV(src),
+#ifdef PMAP_DIRECT_MAP
+ memcpy((void *)PMAP_DIRECT_MAP(dst), (const void *)PMAP_DIRECT_MAP(src),
PAGE_SIZE);
#else
-#error FIX pmap_copy_page!
+#error "no direct map"
#endif
}
@@ -75,7 +80,7 @@ pmap_md_alloc_poolpage(int flags)
vaddr_t
pmap_md_map_poolpage(paddr_t pa, vsize_t len)
{
- return POOL_PHYSTOV(pa);
+ return PMAP_DIRECT_MAP(pa);
}
void
@@ -99,34 +104,17 @@ pmap_md_io_vaddr_p(vaddr_t va)
paddr_t
pmap_md_direct_mapped_vaddr_to_paddr(vaddr_t va)
{
- KASSERT(VM_MAX_KERNEL_ADDRESS <= va && (intptr_t) va < 0);
- const pmap_pdetab_t *ptb = pmap_kernel()->pm_md.md_pdetab;
- pd_entry_t pde;
-
#ifdef _LP64
- pde = ptb->pde_pde[(va >> XSEGSHIFT) & (NPDEPG-1)];
- if ((pde & PTE_V) == 0) {
- return -(paddr_t)1;
- }
- if ((pde & PTE_T) == 0) {
- return pde & ~XSEGOFSET;
- }
- ptb = (const pmap_pdetab_t *)POOL_PHYSTOV(pte_pde_to_paddr(pde));
+ return PMAP_DIRECT_UNMAP(va);
+#else
+#error "no direct map"
#endif
- pde = ptb->pde_pde[(va >> SEGSHIFT) & (NPDEPG-1)];
- if ((pde & PTE_V) == 0) {
- return -(paddr_t)1;
- }
- if ((pde & PTE_T) == 0) {
- return pde & ~SEGOFSET;
- }
- return -(paddr_t)1;
}
vaddr_t
pmap_md_direct_map_paddr(paddr_t pa)
{
- return POOL_PHYSTOV(pa);
+ return PMAP_DIRECT_MAP(pa);
}
void
@@ -161,7 +149,7 @@ pmap_md_pdetab_init(struct pmap *pmap)
pmap_md_direct_mapped_vaddr_to_paddr((vaddr_t)pmap->pm_md.md_pdetab);
}
-// TLB mainenance routines
+/* -------------------------------------------------------------------------- */
tlb_asid_t
tlb_get_asid(void)
@@ -198,7 +186,7 @@ tlb_update_addr(vaddr_t va, tlb_asid_t a
}
u_int
-tlb_record_asids(u_long *ptr)
+tlb_record_asids(u_long *ptr, tlb_asid_t asid_max)
{
memset(ptr, 0xff, PMAP_TLB_NUM_PIDS / (8 * sizeof(u_long)));
ptr[0] = -2UL;
