Module Name: src
Committed By: matt
Date: Tue Mar 9 22:39:32 UTC 2010
Added Files:
src/sys/arch/powerpc/include/booke: Makefile booke_intr.h pte.h spr.h
trap.h vmparam.h
Log Message:
Add initial versions of these for BookE.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/powerpc/include/booke/Makefile \
src/sys/arch/powerpc/include/booke/booke_intr.h \
src/sys/arch/powerpc/include/booke/pte.h \
src/sys/arch/powerpc/include/booke/spr.h \
src/sys/arch/powerpc/include/booke/trap.h \
src/sys/arch/powerpc/include/booke/vmparam.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/powerpc/include/booke/Makefile
diff -u /dev/null src/sys/arch/powerpc/include/booke/Makefile:1.1
--- /dev/null Tue Mar 9 22:39:32 2010
+++ src/sys/arch/powerpc/include/booke/Makefile Tue Mar 9 22:39:32 2010
@@ -0,0 +1,11 @@
+# $NetBSD: Makefile,v 1.1 2010/03/09 22:39:32 matt Exp $
+
+INCSDIR= /usr/include/powerpc/booke
+
+INCS= booke_intr.h \
+ pmap.h pte.h \
+ spr.h \
+ trap.h \
+ vmparam.h
+
+.include <bsd.kinc.mk>
Index: src/sys/arch/powerpc/include/booke/booke_intr.h
diff -u /dev/null src/sys/arch/powerpc/include/booke/booke_intr.h:1.1
--- /dev/null Tue Mar 9 22:39:32 2010
+++ src/sys/arch/powerpc/include/booke/booke_intr.h Tue Mar 9 22:39:32 2010
@@ -0,0 +1,95 @@
+/* $NetBSD: booke_intr.h,v 1.1 2010/03/09 22:39:32 matt Exp $ */
+
+/*-
+ * Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BOOKE_INTR_H_
+#define _BOOKE_INTR_H_
+
+/* Interrupt priority `levels'. */
+#define IPL_NONE 0 /* nothing */
+#define IPL_SOFTCLOCK 1 /* software clock interrupt */
+#define IPL_SOFTBIO 2 /* software block i/o interrupt */
+#define IPL_SOFTNET 3 /* software network interrupt */
+#define IPL_SOFTSERIAL 4 /* software serial interrupt */
+#define IPL_VM 5 /* memory allocation */
+#define IPL_SCHED 6 /* clock */
+#define IPL_HIGH 7 /* everything */
+#define NIPL 8
+
+/* Interrupt sharing types. */
+#define IST_NONE 0 /* none */
+#define IST_PULSE 1 /* pulsed */
+#define IST_EDGE 2 /* edge-triggered */
+#define IST_LEVEL 3 /* level-triggered */
+
+#ifndef _LOCORE
+
+#define CLKF_BASEPRI(frame) ((frame)->cf_ipl == IPL_NONE)
+
+void *intr_establish(int, int, int, int (*)(void *), void *);
+void intr_disestablish(void *);
+void intr_init(void);
+void ext_intr(void); /* for machdep */
+int splraise(int);
+int spllower(int);
+void splx(int);
+void softintr(int);
+
+extern volatile u_int imask[NIPL];
+extern const int mask_clock; /* for clock.c */
+extern const int mask_statclock; /* for clock.c */
+
+#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
+
+typedef int ipl_t;
+typedef struct {
+ ipl_t _ipl;
+} ipl_cookie_t;
+
+static inline ipl_cookie_t
+makeiplcookie(ipl_t ipl)
+{
+
+ return (ipl_cookie_t){._ipl = ipl};
+}
+
+static inline int
+splraiseipl(ipl_cookie_t icookie)
+{
+
+ return splraise(imask[icookie._ipl]);
+}
+
+#include <sys/spl.h>
+
+#define spl0() spllower(0)
+
+#endif /* !_LOCORE */
+#endif /* !_BOOKE_INTR_H_ */
Index: src/sys/arch/powerpc/include/booke/pte.h
diff -u /dev/null src/sys/arch/powerpc/include/booke/pte.h:1.1
--- /dev/null Tue Mar 9 22:39:32 2010
+++ src/sys/arch/powerpc/include/booke/pte.h Tue Mar 9 22:39:32 2010
@@ -0,0 +1,60 @@
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _POWERPC_BOOKE_PTE_H_
+#define _POWERPC_BOOKE_PTE_H_
+
+#ifndef _LOCORE
+typedef __uint32_t pt_entry_t;
+#endif
+
+/*
+ * The PTE format is software and must be translated into the various portions
+ * X W R are separted by single bits so that they can map to the MAS2 bits
+ * UX/UW/UR or SX/SW/SR by a mask and a shift.
+ */
+#define PTE_MAS3_MASK (MAS3_RPN|MAS3_U2)
+#define PTE_MAS2_MASK (MAS2_WIMGE)
+#define PTE_RPN_MASK MAS3_RPN /* MAS3[RPN] */
+#define PTE_RWX_MASK (PTE_xX|PTE_xW|PTE_xR)
+#define PTE_WIRED (MAS3_U0 << 2) /* page is wired (PTE only) */
+#define PTE_xX (MAS3_U0 << 1) /* MAS2[UX] | MAS2[SX] */
+#define PTE_UNSYNCED MAS3_U0 /* page needs isync */
+#define PTE_xW MAS3_U1 /* MAS2[UW] | MAS2[SW] */
+#define PTE_UNMODIFIED MAS3_U2 /* page is unmodified */
+#define PTE_xR MAS3_U3 /* MAS2[UR] | MAS2[SR] */
+#define PTE_RWX_SHIFT 5
+#define PTE_WIMGE_MASK MAS2_WIMGE
+#define PTE_W MAS2_W /* Write-through */
+#define PTE_I MAS2_I /* cache-Inhibited */
+#define PTE_M MAS2_M /* Memory coherence */
+#define PTE_G MAS2_G /* Guarded */
+#define PTE_E MAS2_E /* [Little] Endian */
+
+#endif /* !_POWERPC_BOOKE_PTE_H_ */
Index: src/sys/arch/powerpc/include/booke/spr.h
diff -u /dev/null src/sys/arch/powerpc/include/booke/spr.h:1.1
--- /dev/null Tue Mar 9 22:39:32 2010
+++ src/sys/arch/powerpc/include/booke/spr.h Tue Mar 9 22:39:32 2010
@@ -0,0 +1,402 @@
+/* $NetBSD: spr.h,v 1.1 2010/03/09 22:39:32 matt Exp $ */
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas <m...@3am-software.com>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _POWERPC_BOOKE_SPR_H_
+#define _POWERPC_BOOKE_SPR_H_
+
+#define PVR_MPCe500 0x8020
+#define PVR_MPCe500v2 0x8021
+#define SVR_MPC8548v1 0x80310010
+#define SVR_MPC8543v1 0x80320010
+#define SVR_MPC8548v1plus 0x80310011
+#define SVR_MPC8543v1plus 0x80320011
+#define SVR_MPC8548v2 0x80310020
+#define SVR_MPC8547v2 0x80310120
+#define SVR_MPC8545v2 0x80310220
+#define SVR_MPC8543v2 0x80320020
+#define SVR_MPC8572 0x80300011
+
+/*
+ * Special Purpose Register declarations.
+ *
+ * The first column in the comments indicates which PowerPC architectures the
+ * SPR is valid on - E for BookE series, 4 for 4xx series,
+ * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series.
+ */
+
+#define SPR_PID0 48 /* E4.. 440 Process ID */
+#define SPR_DECAR 54 /* E... Decrementer Auto-reload */
+#define SPR_CSRR0 58 /* E... Critical Save/Restore Reg. 0 */
+#define SPR_CSRR1 59 /* E... Critical Save/Restore Reg. 1 */
+#define SPR_DEAR 61 /* E... Data Exception Address Reg. */
+#define SPR_ESR 62 /* E... Exception Syndrome Register */
+#define ESR_PIL 0x08000000 /* 4: Program ILlegal */
+#define ESR_PPR 0x04000000 /* 5: Program PRivileged */
+#define ESR_PTR 0x02000000 /* 6: Program TRap */
+#define ESR_ST 0x00800000 /* 8: Store operation */
+#define ESR_DLK 0x00200000 /* 10: dcache exception */
+#define ESR_ILK 0x00100000 /* 11: icache exception */
+#define ESR_AP 0x00100000 /* 12: Auxiliary Processor operation exception */
+#define ESR_PUO 0x00100000 /* 13: Program Unimplemented Operation exception */
+#define ESR_BO 0x00020000 /* 14: Byte ordering exception */
+#define ESR_PIE 0x00020000 /* 14: Program Imprecise Exception */
+#define ESR_SPV 0x00000080 /* 24: SPE exception */
+#define ESR_VLEMI 0x00000080 /* 26: VLE exception */
+#define ESR_MIF 0x00000080 /* 30: VLE Misaligned Instruction Fetch */
+#define ESR_XTE 0x00000080 /* 31: eXternal Transaction Error */
+#define SPR_IVPR 63 /* E... Interrupt Vector Prefix Reg. */
+#define SPR_USPRG0 256 /* E4.. User SPR General 0 */
+#define SPR_USPRG3 259 /* E... User SPR General 3 */
+#define SPR_USPRG4 260 /* E... User SPR General 4 */
+#define SPR_USPRG5 261 /* E... User SPR General 5 */
+#define SPR_USPRG6 262 /* E... User SPR General 6 */
+#define SPR_USPRG7 263 /* E... User SPR General 7 */
+#define SPR_RTBL 268 /* E468 Time Base Lower (RO) */
+#define SPR_RTBU 269 /* E468 Time Base Upper (RO) */
+#define SPR_WTBL 284 /* E468 Time Base Lower (WO) */
+#define SPR_WTBU 285 /* E468 Time Base Upper (WO) */
+
+#define SPR_DBSR 304 /* E... Debug Status Register (W1C) */
+#define DBSR_IDE 0x80000000 /* 0: Imprecise debug event */
+#define DBSR_UDE 0x40000000 /* 1: Unconditional debug event */
+#define DBSR_MRR_HARD 0x20000000 /* 2: Most Recent Reset (Hard) */
+#define DBSR_MRR_SOFT 0x10000000 /* 3: Most Recent Reset (Soft) */
+#define DBSR_ICMP 0x08000000 /* 4: Instruction completion debug event */
+#define DBSR_BRT 0x04000000 /* 5: Branch Taken debug event */
+#define DBSR_IRPT 0x02000000 /* 6: Interrupt Taken debug event */
+#define DBSR_TRAP 0x01000000 /* 7: Trap Instruction debug event */
+#define DBSR_IAC1 0x00800000 /* 8: IAC1 debug event */
+#define DBSR_IAC2 0x00400000 /* 9: IAC2 debug event */
+#define DBSR_DR1 0x00080000 /* 12: DAC1 Read debug event */
+#define DBSR_DW1 0x00040000 /* 13: DAC1 Write debug event */
+#define DBSR_DR2 0x00020000 /* 14: DAC2 Read debug event */
+#define DBSR_DW2 0x00010000 /* 15: DAC2 Write debug event */
+#define DBSR_RET 0x00008000 /* 16: Return debug event */
+#define SPR_DBCR0 308 /* E... Debug Control Register 0 */
+#define DBCR0_EDM 0x80000000 /* 0: External Debug Mode */
+#define DBCR0_IDM 0x40000000 /* 1: Internal Debug Mode */
+#define DBCR0_RST_MASK 0x30000000 /* 2..3: ReSeT */
+#define DBCR0_RST_NONE 0x00000000 /* No action */
+#define DBCR0_RST_CORE 0x10000000 /* Core reset */
+#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */
+#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */
+#define DBCR0_IC 0x08000000 /* 4: Instruction Completion debug event */
+#define DBCR0_BT 0x04000000 /* 5: Branch Taken debug event */
+#define DBCR0_EDE 0x02000000 /* 6: Exception Debug Event */
+#define DBCR0_TDE 0x01000000 /* 7: Trap Debug Event */
+#define DBCR0_IA1 0x00800000 /* 8: IAC (Instruction Address Compare) 1 debug event */
+#define DBCR0_IA2 0x00400000 /* 9: IAC 2 debug event */
+#define DBCR0_IA12 0x00200000 /* 10: Instruction Address Range Compare 1-2 */
+#define DBCR0_IA12X 0x00100000 /* 11: IA12 eXclusive */
+#define DBCR0_IA3 0x00080000 /* 12: IAC 3 debug event */
+#define DBCR0_DAC1_LOAD 0x00080000 /* 12: DAC (Data Address Compare) 1 load event (e500) */
+#define DBCR0_IA4 0x00040000 /* 13: IAC 4 debug event */
+#define DBCR0_DAC1_STORE 0x00040000 /* 13: DAC (Data Address Compare) 1 store event (e500) */
+#define DBCR0_IA34 0x00020000 /* 14: Instruction Address Range Compare 3-4 */
+#define DBCR0_DAC2_LOAD 0x00020000 /* 14: DAC 2 load event (e500) */
+#define DBCR0_IA34X 0x00010000 /* 15: IA34 eXclusive */
+#define DBCR0_DAC2_STORE 0x00010000 /* 15: DAC 2 store event (e500) */
+#define DBCR0_IA12T 0x00008000 /* 16: Instruction Address Range Compare 1-2 range Toggle */
+#define DBCR0_RET 0x00008000 /* 16: Return debug event (e500) */
+#define DBCR0_IA34T 0x00004000 /* 17: Instruction Address Range Compare 3-4 range Toggle */
+#define DBCR0_FT 0x00000001 /* 31: Freeze Timers on debug event */
+#define SPR_DBCR1 309 /* E... Debug Control Register 1 */
+#define SPR_DBCR2 310 /* E... Debug Control Register 2 */
+#define SPR_IAC1 312 /* E... Instruction Address Compare 1 */
+#define SPR_IAC2 313 /* E... Instruction Address Compare 2 */
+#define SPR_IAC3 314 /* E... Instruction Address Compare 3 */
+#define SPR_IAC4 315 /* E... Instruction Address Compare 4 */
+#define SPR_DAC1 316 /* E... Data Address Compare 1 */
+#define SPR_DAC2 317 /* E... Data Address Compare 2 */
+#define SPR_TSR 336 /* E... Timer Status Register */
+#define TSR_ENW 0x80000000 /* Enable Next Watchdog (W1C) */
+#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status (W1C) */
+#define TSR_WRS 0x30000000 /* Watchdog Reset Status (W1C) */
+#define TSR_DIS 0x08000000 /* Decementer Interrupt Status (W1C) */
+#define TSR_FIS 0x04000000 /* Fixed-interval Interrupt Status (W1C) */
+#define SPR_TCR 340 /* E... Timer Control Register */
+#define TCR_WP 0xc0000000 /* Watchdog Period */
+#define TCR_WRC 0x30000000 /* Watchdog Timer Reset Control */
+#define TCR_WIE 0x08000000 /* Watchdog Time Interrupt Enable */
+#define TCR_DIE 0x04000000 /* Decremnter Interrupt Enable */
+#define TCR_FP 0x03000000 /* Fixed-interval Timer Period */
+#define TCR_FIE 0x00800000 /* Fixed-interval Interrupt Enable */
+#define TCR_ARE 0x00400000 /* Auto-reload Enable */
+#define TCR_WPEXT 0x80000000 /* Watchdog Period Extension */
+#define TCR_FPEXT 0x80000000 /* Fixed-interval Period Extension */
+
+#define SPR_IVOR0 400 /* E... Critical input interrupt offset */
+#define SPR_IVOR1 401 /* E... Machine check interrupt offset */
+#define SPR_IVOR2 402 /* E... Data storage interrupt offset */
+#define SPR_IVOR3 403 /* E... Instruction storage interrupt offset */
+#define SPR_IVOR4 404 /* E... External input interrupt offset */
+#define SPR_IVOR5 405 /* E... Alignment interrupt offset */
+#define SPR_IVOR6 406 /* E... Program interrupt offset */
+#define SPR_IVOR8 408 /* E... Syscall call interrupt offset */
+#define SPR_IVOR10 410 /* E... Decrementer interrupt offset */
+#define SPR_IVOR11 411 /* E... Fixed-interval timer interrupt offset */
+#define SPR_IVOR12 412 /* E... Watchdog timer interrupt offset */
+#define SPR_IVOR13 413 /* E... Data TLB error interrupt offset */
+#define SPR_IVOR14 414 /* E... Instruction TLB error interrupt offset */
+#define SPR_IVOR15 415 /* E... Debug interrupt offset */
+#define SPR_SPEFSCR 512 /* E... Signal processing and embedded floating-point status and control register */
+#define SPEFSCR_SOVH 0x80000000 /* 0: Summary Integer Overflow High */
+#define SPEFSCR_OVH 0x40000000 /* 1: Integer Overflow High */
+#define SPEFSCR_FGH 0x20000000 /* 2: Embedded Floating-Point Guard Bit High */
+#define SPEFSCR_FXH 0x10000000 /* 3: Embedded Floating-Point Sticky Bit High */
+#define SPEFSCR_FINVH 0x08000000 /* 4: Embedded Floating-Point Invalid Operation High */
+#define SPEFSCR_FDBZH 0x04000000 /* 5: Embedded Floating-Point Divide By Zero Error High */
+#define SPEFSCR_FUNFH 0x02000000 /* 6: Embedded Floating-Point Underflow Error High */
+#define SPEFSCR_FOVFH 0x01000000 /* 7: Embedded Floating-Point Overflow Error High */
+#define SPEFSCR_FINXS 0x00200000 /* 10: Embedded Floating-Point Inexact Sticky Bit */
+#define SPEFSCR_FINVS 0x00100000 /* 11: Embedded Floating-Point Invalid Operation Sticky Bit */
+#define SPEFSCR_FDBZS 0x00080000 /* 12: Embedded Floating-Point Divide By Zero Sticky Bit */
+#define SPEFSCR_FUNFS 0x00040000 /* 13: Embedded Floating-Point Underflow Sticky Bit */
+#define SPEFSCR_FOVFS 0x00020000 /* 14: Embedded Floating-Point Overflow Sticky Bit */
+#define SPEFSCR_MODE 0x00010000 /* 15: Embedded Floating-Point Mode */
+#define SPEFSCR_SOV 0x80000000 /* 16: Summary Integer Overflow */
+#define SPEFSCR_OV 0x00004000 /* 17: Integer Overflow */
+#define SPEFSCR_FG 0x00002000 /* 18: Embedded Floating-Point Guard Bit */
+#define SPEFSCR_FX 0x00001000 /* 19: Embedded Floating-Point Sticky Bit */
+#define SPEFSCR_FINV 0x00000800 /* 20: Embedded Floating-Point Invalid Operation */
+#define SPEFSCR_FDBZ 0x00000400 /* 21: Embedded Floating-Point Divide By Zero Error */
+#define SPEFSCR_FUNF 0x00000200 /* 22: Embedded Floating-Point Underflow Error */
+#define SPEFSCR_FOVF 0x00000100 /* 23: Embedded Floating-Point Overflow Error */
+#define SPEFSCR_FINXE 0x00000040 /* 25: Embedded Floating-Point Inexact Execption Enable */
+#define SPEFSCR_FINVE 0x00000020 /* 26: Embedded Floating-Point Invalid Operation/Input Error Execption Enable */
+#define SPEFSCR_FDBZE 0x00000010 /* 27: Embedded Floating-Point Divide By Zero Exception Enable */
+#define SPEFSCR_FUNFE 0x00000008 /* 28: Embedded Floating-Point Underflow Exception Enable */
+#define SPEFSCR_FOVFE 0x00000004 /* 29: Embedded Floating-Point Overflow Exception Enable */
+#define SPEFSCR_FRMC_MASK 0x00000003 /* 30..31: Embedded Floating-Point Rounding Mode Control */
+#define SPEFSCR_FRMC_DOWNWARD 0x00000003 /* Round toward -infinity */
+#define SPEFSCR_FRMC_UPWARD 0x00000002 /* Round toward +infinity */
+#define SPEFSCR_FRMC_TOWARDZERO 0x00000001 /* Round toward zero */
+#define SPEFSCR_FRMC_TONEAREST 0x00000000 /* Round to nearest */
+#define SPR_BBEAR 513 /* E... Brach buffer entry addr register */
+#define SPR_BBTAR 514 /* E... Brach buffer target addr register */
+#define SPR_L1CFG0 515 /* E... L1 Cache Configuration Register 0 */
+#define SPR_L1CFG1 516 /* E... L1 Cache Configuration Register 1 */
+#define L1CFG_CARCH_GET(n) (((n) >> 30) & 3)
+#define L1CFG_CARCH_HARVARD 0
+#define L1CFG_CARCH_UNIFIED 1
+#define L1CFG_CBSIZE_GET(n) (((n) >> 23) & 3)
+#define L1CFG_CBSIZE_32B 0
+#define L1CFG_CBSIZE_64B 1
+#define L1CFG_CREPL_GET(n) (((n) >> 21) & 3)
+#define L1CFG_CREPL_TRUE_LRU 0
+#define L1CFG_CREPL_PSEUDO_LRU 1
+#define L1CFG_CLA_P(n) (((n) >> 20) & 1)
+#define L1CFG_CPA_P(n) (((n) >> 19) & 1)
+#define L1CFG_CNWAY_GET(n) ((((n) >> 13) & 0xff) + 1)
+#define L1CFG_CSIZE_GET(n) ((((n) >> 0) & 0x7ff) << 10)
+#define SPR_ATBL 526 /* E... Alternate Time Base Lower */
+#define SPR_ATBU 527 /* E... Alternate Time Base Upper */
+#define SPR_IVOR32 528 /* E... SPE unavailable interrupt offset */
+#define SPR_IVOR33 529 /* E... Floating-point data exception interrupt offset */
+#define SPR_IVOR34 530 /* E... Floating-point round exception interrupt offset */
+#define SPR_IVOR35 531 /* E... Performance monitor interrupt offset */
+#define SPR_MCARU 569 /* E... Machine check address register upper */
+#define SPR_MCSRR0 570 /* E... Machine check save/restore register 0 */
+#define SPR_MCSRR1 571 /* E... Machine check save/restore register 1 */
+#define SPR_MCSR 572 /* E... Machine check syndrome register */
+#define MCSR_MCP 0x80000000 /* 0: Machine Check Input Pin */
+#define MCSR_ICPERR 0x40000000 /* 1: Instruction Cache Parity Error */
+#define MCSR_DCP_PERR 0x20000000 /* 2: Data Cache Push Parity Error */
+#define MCSR_DCPERR 0x10000000 /* 3: Data Cache Parity Error */
+#define MCSR_NMI 0x00100000 /* 12: non maskable interrupt */
+#define MCSR_MAV 0x00080000 /* 13: MCAR address valid */
+#define MCSR_MEA 0x00040000 /* 14: MCAR [is an] effective address */
+#define MCSR_BUS_IAERR 0x00000080 /* 24: Bus Instruction Address Error */
+#define MCSR_BUS_RAERR 0x00000040 /* 25: Bus Read Address Error */
+#define MCSR_BUS_WAERR 0x00000020 /* 26: Bus Write Address Error */
+#define MCSR_BUS_IBERR 0x00000010 /* 27: Bus Instruction Data Bus Error */
+#define MCSR_BUS_RBERR 0x00000008 /* 28: Bus Read Data Bus Error */
+#define MCSR_BUS_WBERR 0x00000004 /* 29: Bus Write Data Bus Error */
+#define MCSR_BUS_IPERR 0x00000002 /* 30: Bus Instruction Parity Error */
+#define MCSR_BUS_RPERR 0x00000001 /* 31: Bus Read Parity Error */
+#define SPR_MCAR 573 /* E... Machine check address register */
+#define SPR_MAS0 624 /* E... MAS Register 0 */
+#define MAS0_TLBSEL 0x03000000 /* Select TLB<n> for access */
+#define MAS0_TLBSEL_TLB3 0x03000000 /* Select TLB3 for access */
+#define MAS0_TLBSEL_TLB2 0x02000000 /* Select TLB2 for access */
+#define MAS0_TLBSEL_TLB1 0x01000000 /* Select TLB1 for access */
+#define MAS0_TLBSEL_TLB0 0x00000000 /* Select TLB0 for access */
+#define MASX_TLBSEL_GET(n) (((n) >> 28) & 3)
+#define MASX_TLBSEL_MAKE(n) (((n) & 3) << 28)
+#define MAS0_ESEL 0x0fff0000 /* entry (way) select for tlbwe */
+#define MAS0_ESEL_GET(n) (((n) >> 16) & 4095)
+#define MAS0_ESEL_MAKE(n) (((n) & 4095) << 16)
+#define MAS0_NV 0x00000fff /* next victim fr TLB0[NV] */
+#define SPR_MAS1 625 /* E... MAS Register 1 */
+#define MAS1_V 0x80000000 /* TLB Valid Bit */
+#define MAS1_IPROT 0x40000000 /* Invalidate Protect */
+#define MAS1_TID 0x0fff0000 /* Translation Identity */
+#define MASX_TID_GET(n) (((n) >> 16) & 4095)
+#define MASX_TID_MAKE(n) (((n) & 4095) << 16)
+#define MAS1_TS 0x00001000 /* Translation Space [IS/DS MSR] */
+#define MAS1_TS_SHIFT 12
+#define MAS1_TSIZE 0x00000f00 /* Translation Size (4KB**tsize) */
+#define MASX_TSIZE_GET(n) (((n) >> 8) & 15)
+#define MASX_TSIZE_MAKE(n) (((n) & 15) << 8)
+#define SPR_MAS2 626 /* E... MAS Register 2 */
+#define MAS2_EPN 0xfffff000 /* Effective Page Number */
+#define MAS2_EPN_GET(n) (((n) >> 12) & 1048575)
+#define MAS2_EPN_MAKE(n) (((n) & 1048575) << 12)
+#define MAS2_X0 0x00000040 /* Impl. dependent page attr. */
+#define MAS2_ACM 0x000000c0 /* Alternate Coherency Mode. */
+#define MAS2_X1 0x00000020 /* Impl. dependent page attr. */
+#define MAS2_VLE 0x00000020 /* VLE mode. */
+#define MAS2_WIMGE 0x0000001f /* Mask of next 5 bits */
+#define MAS2_W 0x00000010 /* Write-through */
+#define MAS2_I 0x00000008 /* cache-Inhibited */
+#define MAS2_M 0x00000004 /* Memory coherency required */
+#define MAS2_G 0x00000002 /* Gaurded */
+#define MAS2_E 0x00000001 /* [little] Endianness */
+#define SPR_MAS3 627 /* E... MAS Register 3 */
+#define MAS3_RPN 0xfffff000 /* Real Page Number */
+#define MAS3_RPN_GET(n) (((n) >> 12) & 1048575)
+#define MAS3_RPN_MAKE(n) (((n) & 1048575) << 12)
+#define MAS3_U0 0x00000200 /* User attribute 0 */
+#define MAS3_U1 0x00000100 /* User attribute 1 */
+#define MAS3_U2 0x00000080 /* User attribute 2 */
+#define MAS3_U3 0x00000040 /* User attribute 3 */
+#define MAS3_UX 0x00000020 /* User execute permission */
+#define MAS3_SX 0x00000010 /* System execute permission */
+#define MAS3_UW 0x00000008 /* User write permission */
+#define MAS3_SW 0x00000004 /* System write permission */
+#define MAS3_UR 0x00000002 /* User read permission */
+#define MAS3_SR 0x00000001 /* System read permission */
+#define SPR_MAS4 628 /* E... MAS Register 4 */
+#define MAS4_TLBSELD 0x30000000 /* TLBSEL default value */
+#define MAS4_TIDSELD 0x0fff0000 /* select TID default value */
+#define MAS4_TSIZED 0x00000f00 /* TSIZE default value */
+#define MAS4_ACMD 0x000000c0 /* Alternate Coherency Mode. */
+#define MAS4_X0D 0x00000040 /* default Impl. dep. page attr. */
+#define MAS4_VLED 0x00000020 /* VLE mode. */
+#define MAS4_X1D 0x00000020 /* default Impl. dep. page attr. */
+#define MAS4_WD 0x00000010 /* default Write-through */
+#define MAS4_ID 0x00000008 /* default Cache-inhibited */
+#define MAS4_MD 0x00000004 /* default Memory coherency req. */
+#define MAS4_GD 0x00000002 /* default Gaurded */
+#define MAS4_ED 0x00000001 /* default [little] Endianness */
+#define SPR_MAS6 630 /* E... MAS Register 6 (TLB Seach CTX) */
+#define MAS6_SPID0 0x0fff0000 /* PID used with tlbsx */
+#define MAS6_SPID0_SHIFT 16
+#define MAS6_SAS 0x00000001 /* Address space (IS/DS MSR) ... */
+#define MAS6_SAS_USER 0x00000001 /* Address space (IS/DS MSR) ... */
+#define SPR_PID1 633 /* E... PID Register 1 */
+#define SPR_PID2 634 /* E... PID Register 2 */
+#define SPR_TLB0CFG 688 /* E... TLB Configuration Register 0 */
+#define SPR_TLB1CFG 689 /* E... TLB Configuration Register 1 */
+#define TLBCFG_ASSOC(n) (((n) >> 24) & 0xff) /* assoc of tlb */
+#define TLBCFG_MINSIZE(n) (((n) >> 20) & 0x0f) /* minpagesize */
+#define TLBCFG_MAXSIZE(n) (((n) >> 16) & 0x0f) /* maxpagesize */
+#define TLBCFG_IPROT_P(n) (((n) >> 15) & 0x01)
+#define TLBCFG_AVAIL_P(n) (((n) >> 14) & 0x01) /* variable page size */
+#define TLBCFG_NENTRY(n) (((n) >> 0) & 0xfff) /* # entrys */
+#define SPR_MAS7 944 /* E... MAS Register 7 */
+#define MAS7_RPNHI 0x00000004 /* bits 32-35 of RPN */
+#define SPR_HID0 1008
+#define SPR_HID1 1009
+#define SPR_L1CSR0 1010 /* E... L1 Cache Control and Status Register 0 (Data) */
+#define SPR_L1CSR1 1011 /* E... L1 Cache Control and Status Register 1 (Instruction) */
+#define L1CSR_CPE 0x00010000 /* 15: Cache Parity Error */
+#define L1CSR_CPI 0x00008000 /* 16: Cache Parity Injection Enable */
+#define L1CSR_CSLC 0x00000800 /* 20: Cache Snoop Lock Clear */
+#define L1CSR_CUL 0x00000400 /* 21: Cache Unable to Lock (W0C) */
+#define L1CSR_CLO 0x00000200 /* 22: Cache Lock Overflow (W0C) */
+#define L1CSR_CLFR 0x00000100 /* 23: Cache Lock Bits Flash Reset */
+#define L1CSR_CFI 0x00000002 /* 30: Cache Flash Invalidate */
+#define L1CSR_CE 0x00000001 /* 31: Cache Enable */
+#define SPR_MMUCSR0 1012 /* E... MMU Control and Status Register 0 */
+#define MMUCSR0_TLB2_FI 0x00000040 /* TLB2 Flash Invalidate */
+#define MMUCSR0_TLB3_FI 0x00000020 /* TLB3 Flash Invalidate */
+#define MMUCSR0_TLB0_FI 0x00000004 /* TLB0 Flash Invalidate */
+#define MMUCSR0_TLB1_FI 0x00000002 /* TLB1 Flash Invalidate */
+#define SPR_BUCSR 1013 /* E... Branch Unit Control and Status Register */
+#define SPR_MMUCFG 1015 /* E... MMU Configuration Register */
+#define MMUCFG_RASIZE_GET(n) (((n) >> 17) & 127) /* Real Address Size */
+#define MMUCFG_NPIDS_GET(n) (((n) >> 11) & 15) /* # of PID registers */
+#define MMUCFG_PIDSIZE_GET(n) (((n) >> 6) & 31) /* PID is PIDSIZE+1 bits wide */
+#define MMUCFG_NTLBS_GET(n) (((n) >> 2) & 3) /* NTLBS is max value of MAS0[TLBSEL] */
+#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
+#define MMUCFG_MAVN_V1 0
+#define SPR_SVR 1023 /* E... System Version Register */
+
+#define PMR_PMC0 16
+#define PMR_PMC1 17
+#define PMR_PMC2 18
+#define PMR_PMC3 19
+#define PMR_PMLCa0 144
+#define PMR_PMLCa1 145
+#define PMR_PMLCa2 146
+#define PMR_PMLCa3 147
+#define PMLCa_FC 0x80000000 /* 0: Freeze Counter */
+#define PMLCa_FCS 0x40000000 /* 1: Freeze Counter In Super */
+#define PMLCa_FCU 0x20000000 /* 2: Freeze Counter In User */
+#define PMLCa_FCM1 0x10000000 /* 3: Freeze Counter While Mark=1 */
+#define PMLCa_FCM0 0x08000000 /* 4: Freeze Counter While Mark=0 */
+#define PMLCa_CE 0x04000000 /* 5: Condition Enable */
+#define PMLCa_EVENT 0x007f0000 /* 9..15: Event */
+#define PMLCa_EVENT_GET(n) (((n) >> 16) & 127)
+#define PMLCa_EVENT_MAKE(n) (((n) & 127) << 16)
+
+#define PMR_PMLCb0 272
+#define PMR_PMLCb1 273
+#define PMR_PMLCb2 274
+#define PMR_PMLCb3 275
+#define PMLCb_THRESHMUL 0x00007f00 /* 21..23: multiply threshold by 2**<n> */
+#define PMLCb_THRESHMUL_GET(n) (((n) >> 16) & 127)
+#define PMLCb_THRESHMUL_MAKE(n) (((n) & 127) << 16)
+#define PMLCb_THRESHOLD 0x0000003f /* 26..31: threshold */
+#define PMLCb_THRESHOLD_GET(n) (((n) >> 0) & 63)
+#define PMLCb_THRESHOLD_MAKE(n) (((n) & 63) << 0)
+#define PMR_PMGC0 400
+#define PMGC0_FAC 0x80000000 /* 0: Freeze All Counters */
+#define PMGC0_PMIE 0x40000000 /* 1: Performance Monitor Interrupt Enable */
+#define PMGC0_FCECE 0x40000000 /* 1: Freeze count on enabled condition or event */
+#define PMGC0_TBSEL 0x00001800 /* 19..20: Time base selector */
+#define PMGC0_TBEE 0x00000100 /* 23: Time base transition event exception enable */
+
+#define PMR_UPMC0 (PMR_PMC0 - 16)
+#define PMR_UPMC1 (PMR_PMC1 - 16)
+#define PMR_UPMC2 (PMR_PMC2 - 16)
+#define PMR_UPMC3 (PMR_PMC3 - 16)
+#define PMR_UPMLCa0 (PMR_PMLCa0 - 16)
+#define PMR_UPMLCa1 (PMR_PMLCa1 - 16)
+#define PMR_UPMLCa2 (PMR_PMLCa2 - 16)
+#define PMR_UPMLCa3 (PMR_PMLCa3 - 16)
+#define PMR_UPMLCb0 (PMR_PMLCb0 - 16)
+#define PMR_UPMLCb1 (PMR_PMLCb1 - 16)
+#define PMR_UPMLCb2 (PMR_PMLCb2 - 16)
+#define PMR_UPMLCb3 (PMR_PMLCb3 - 16)
+#define PMR_UPMGC0 (PMR_PMGC0 - 16)
+
+#endif /* !_POWERPC_SPR_H_ */
Index: src/sys/arch/powerpc/include/booke/trap.h
diff -u /dev/null src/sys/arch/powerpc/include/booke/trap.h:1.1
--- /dev/null Tue Mar 9 22:39:32 2010
+++ src/sys/arch/powerpc/include/booke/trap.h Tue Mar 9 22:39:32 2010
@@ -0,0 +1,57 @@
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _POWERPC_BOOKE_TRAP_H_
+#define _POWERPC_BOOKE_TRAP_H_
+
+enum ppc_booke_exceptions {
+ T_CRITIAL_INPUT=0,
+ T_MACHINE_CHECK=1,
+ T_DSI=2,
+ T_ISI=3,
+ T_INTERRUPT=4,
+ T_ALIGNMENT=5,
+ T_PROGRAM=6,
+ T_FP_UNAVAILABLE=7,
+ T_SYSTEM_CALL=8,
+ T_AP_UNAVAILABLE=9,
+ T_DECREMENTER=10,
+ T_FIXED_INTERVAL=11,
+ T_WATCHDOG=12,
+ T_DATA_TLB_ERROR=13,
+ T_INSTRUCTION_TLB_ERROR=14,
+ T_DEBUG=15,
+ T_SPE_UNAVAILABLE=32,
+ T_EMBEDDED_FP_DATA=33,
+ T_EMBEDDED_FP_ROUND=34,
+ T_EMBEDDED_PERF_MONITOR=35,
+ T_AST=64,
+};
+
+#endif /* _POWERPC_BOOKE_TRAP_H_ */
Index: src/sys/arch/powerpc/include/booke/vmparam.h
diff -u /dev/null src/sys/arch/powerpc/include/booke/vmparam.h:1.1
--- /dev/null Tue Mar 9 22:39:32 2010
+++ src/sys/arch/powerpc/include/booke/vmparam.h Tue Mar 9 22:39:32 2010
@@ -0,0 +1,147 @@
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry, LLC.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _POWERPC_BOOKE_VMPARAM_H_
+#define _POWERPC_BOOKE_VMPARAM_H_
+
+/*
+ * Most of the definitions in this can be overriden by a machine-specific
+ * vmparam.h if required. Otherwise a port can just include this file
+ * get the right thing to happen.
+ */
+
+/*
+ * BookE processors have 4K pages. Override the PAGE_* definitions to be
+ * compile-time constants.
+ */
+#define PAGE_SHIFT 12
+#define PAGE_SIZE (1 << PAGE_SHIFT)
+#define PAGE_MASK (PAGE_SIZE - 1)
+
+#ifndef USRSTACK
+#define USRSTACK VM_MAXUSER_ADDRESS
+#endif
+
+#ifndef MAXTSIZ
+#define MAXTSIZ (2*256*1024*1024) /* maximum text size */
+#endif
+
+#ifndef MAXDSIZ
+#define MAXDSIZ (13*256*1024*1024) /* maximum data size */
+#endif
+
+#ifndef MAXSSIZ
+#define MAXSSIZ (1*256*1024*1024-PAGE_SIZE) /* maximum stack size */
+#endif
+
+#ifndef DFLDSIZ
+#define DFLDSIZ (256*1024*1024) /* default data size */
+#endif
+
+#ifndef DFLSSIZ
+#define DFLSSIZ (2*1024*1024) /* default stack size */
+#endif
+
+/*
+ * Default number of pages in the user raw I/O map.
+ */
+#ifndef USRIOSIZE
+#define USRIOSIZE 1024
+#endif
+
+/*
+ * The number of seconds for a process to be blocked before being
+ * considered very swappable.
+ */
+#ifndef MAXSLP
+#define MAXSLP 20
+#endif
+
+/*
+ * Some system constants
+ */
+
+#define VM_MIN_ADDRESS ((vaddr_t) 0)
+#define VM_MAXUSER_ADDRESS ((vaddr_t) -PAGE_SIZE)
+#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS
+#define VM_MIN_KERNEL_ADDRESS ((vaddr_t) 0xe4000000)
+#define VM_MAX_KERNEL_ADDRESS ((vaddr_t) 0xfefff000)
+
+/*
+ * The address to which unspecified mapping requests default
+ * Put the stack in it's own segment and start mmaping at the
+ * top of the next lower segment.
+ */
+#ifdef _KERNEL_OPT
+#include "opt_uvm.h"
+#endif
+#define __USE_TOPDOWN_VM
+#define VM_DEFAULT_ADDRESS(da, sz) \
+ (((VM_MAXUSER_ADDRESS - MAXSSIZ) - round_page(sz))
+
+#ifndef VM_PHYSSEG_MAX
+#define VM_PHYSSEG_MAX 16
+#endif
+#define VM_PHYSSEG_STRAT VM_PSTRAT_BIGFIRST
+#define VM_PHYSSEG_NOADD
+
+#ifndef VM_PHYS_SIZE
+#define VM_PHYS_SIZE (USRIOSIZE * PAGE_SIZE)
+#endif
+
+#define VM_NFREELIST 2 /* 16 distinct memory segments */
+#define VM_FREELIST_DEFAULT 0
+#define VM_FREELIST_FIRST16 1
+#define VM_FREELIST_MAX 2
+
+#ifndef _LOCORE
+
+#define __HAVE_VM_PAGE_MD
+
+struct pv_entry {
+ struct pv_entry *pv_next;
+ struct pmap *pv_pmap;
+ vaddr_t pv_va;
+};
+
+struct vm_page_md {
+ struct pv_entry mdpg_pvlist;
+ unsigned int mdpg_attrs;
+};
+
+#define VM_MDPAGE_INIT(pg) do { \
+ (pg)->mdpage.mdpg_pvlist.pv_next = NULL; \
+ (pg)->mdpage.mdpg_pvlist.pv_pmap = NULL; \
+ (pg)->mdpage.mdpg_pvlist.pv_va = 0; \
+ (pg)->mdpage.mdpg_attrs = 0; \
+} while (/*CONSTCOND*/0)
+
+#endif /* _LOCORE */
+
+#endif /* _POWERPC_BOOKE_VMPARAM_H_ */
