Module Name: src
Committed By: matt
Date: Sun Feb 28 04:04:46 UTC 2010
Modified Files:
src/sys/arch/cobalt/cobalt [matt-nb5-mips64]: interrupt.c machdep.c
src/sys/arch/cobalt/conf [matt-nb5-mips64]: GENERIC std.cobalt
src/sys/arch/cobalt/include [matt-nb5-mips64]: intr.h
Added Files:
src/sys/arch/cobalt/conf [matt-nb5-mips64]: GENERIC64
src/sys/arch/cobalt/include [matt-nb5-mips64]: netbsd32_machdep.h
Log Message:
Adapt to new common interrupts.
Enable cobalt64
To generate a diff of this commit:
cvs rdiff -u -r1.3.16.1 -r1.3.16.2 src/sys/arch/cobalt/cobalt/interrupt.c
cvs rdiff -u -r1.98.10.2 -r1.98.10.3 src/sys/arch/cobalt/cobalt/machdep.c
cvs rdiff -u -r1.119 -r1.119.6.1 src/sys/arch/cobalt/conf/GENERIC
cvs rdiff -u -r0 -r1.1.4.2 src/sys/arch/cobalt/conf/GENERIC64
cvs rdiff -u -r1.13 -r1.13.80.1 src/sys/arch/cobalt/conf/std.cobalt
cvs rdiff -u -r1.32.12.1 -r1.32.12.2 src/sys/arch/cobalt/include/intr.h
cvs rdiff -u -r0 -r1.1.4.2 src/sys/arch/cobalt/include/netbsd32_machdep.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/cobalt/cobalt/interrupt.c
diff -u src/sys/arch/cobalt/cobalt/interrupt.c:1.3.16.1 src/sys/arch/cobalt/cobalt/interrupt.c:1.3.16.2
--- src/sys/arch/cobalt/cobalt/interrupt.c:1.3.16.1 Fri Feb 5 07:39:52 2010
+++ src/sys/arch/cobalt/cobalt/interrupt.c Sun Feb 28 04:04:46 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.3.16.1 2010/02/05 07:39:52 matt Exp $ */
+/* $NetBSD: interrupt.c,v 1.3.16.2 2010/02/28 04:04:46 matt Exp $ */
/*-
* Copyright (c) 2006 Izumi Tsutsui. All rights reserved.
@@ -79,7 +79,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.3.16.1 2010/02/05 07:39:52 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.3.16.2 2010/02/28 04:04:46 matt Exp $");
+
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/malloc.h>
@@ -139,11 +141,27 @@
static int icu_intr(void *);
static void icu_set(void);
+static const struct ipl_sr_map cobalt_ipl_sr_map = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_1
+ | MIPS_INT_MASK_2 | MIPS_INT_MASK_3
+ | MIPS_INT_MASK_4,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
+};
+
void
intr_init(void)
{
int i;
+ ipl_sr_map = cobalt_ipl_sr_map;
/*
* Initialize CPU interrupts.
*/
@@ -388,109 +406,65 @@
}
}
+static void inline
+intr_handle(struct cpu_intrhead *intr)
+{
+ struct cobalt_intrhand * const ih = &intr->intr_ih;
+ if (__predict_true(ih->ih_func != NULL)
+ && __predict_true((*ih->ih_func)(ih->ih_arg))) {
+ intr->intr_evcnt.ev_count++;
+ }
+}
+
void
-cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
- struct clockframe cf;
- struct cobalt_intrhand *ih;
- struct cpu_info *ci;
- uint32_t handled;
+ uint32_t pending;
+ int ipl;
- handled = 0;
- ci = curcpu();
- ci->ci_idepth++;
uvmexp.intrs++;
- if (ipending & MIPS_INT_MASK_5) {
- /* call the common MIPS3 clock interrupt handler */
- cf.pc = pc;
- cf.sr = status;
- mips3_clockintr(&cf);
-
- handled |= MIPS_INT_MASK_5;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
-
- if (__predict_false(ipending & MIPS_INT_MASK_0)) {
- /* GT64x11 timer0 */
- volatile uint32_t *irq_src =
- (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_INTR_CAUSE);
-
- if (__predict_true((*irq_src & T0EXP) != 0)) {
- /* GT64x11 timer is no longer used for hardclock(9) */
- *irq_src = 0;
+ while (ppl < (ipl = splintr(&pending))) {
+ splx(ipl);
+ if (pending & MIPS_INT_MASK_5) {
+ struct clockframe cf;
+ /* call the common MIPS3 clock interrupt handler */
+ cf.pc = pc;
+ cf.sr = status;
+ cf.intr = (curcpu()->ci_idepth > 1);
+ mips3_clockintr(&cf);
}
- handled |= MIPS_INT_MASK_0;
- }
- if (ipending & MIPS_INT_MASK_3) {
- /* 16650 serial */
- ih = &cpu_intrtab[3].intr_ih;
- if (__predict_true(ih->ih_func != NULL)) {
- if (__predict_true((*ih->ih_func)(ih->ih_arg))) {
- cpu_intrtab[3].intr_evcnt.ev_count++;
+ if (__predict_false(pending & MIPS_INT_MASK_0)) {
+ /* GT64x11 timer0 */
+ volatile uint32_t *irq_src =
+ (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_INTR_CAUSE);
+
+ if (__predict_true((*irq_src & T0EXP) != 0)) {
+ /* GT64x11 timer is no longer used for hardclock(9) */
+ *irq_src = 0;
}
}
- handled |= MIPS_INT_MASK_3;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
- if (ipending & MIPS_INT_MASK_1) {
- /* tulip primary */
- ih = &cpu_intrtab[1].intr_ih;
- if (__predict_true(ih->ih_func != NULL)) {
- if (__predict_true((*ih->ih_func)(ih->ih_arg))) {
- cpu_intrtab[1].intr_evcnt.ev_count++;
- }
+ if (pending & MIPS_INT_MASK_3) {
+ /* 16650 serial */
+ intr_handle(&cpu_intrtab[3]);
}
- handled |= MIPS_INT_MASK_1;
- }
- if (ipending & MIPS_INT_MASK_2) {
- /* tulip secondary */
- ih = &cpu_intrtab[2].intr_ih;
- if (__predict_true(ih->ih_func != NULL)) {
- if (__predict_true((*ih->ih_func)(ih->ih_arg))) {
- cpu_intrtab[2].intr_evcnt.ev_count++;
- }
- }
- handled |= MIPS_INT_MASK_2;
- }
- if (ipending & MIPS_INT_MASK_4) {
- /* ICU interrupts */
- ih = &cpu_intrtab[4].intr_ih;
- if (__predict_true(ih->ih_func != NULL)) {
- if (__predict_true((*ih->ih_func)(ih->ih_arg))) {
- cpu_intrtab[4].intr_evcnt.ev_count++;
- }
+ if (pending & MIPS_INT_MASK_1) {
+ /* tulip primary */
+ intr_handle(&cpu_intrtab[1]);
}
- handled |= MIPS_INT_MASK_4;
- }
- cause &= ~handled;
- _splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
- ci->ci_idepth--;
-
-#ifdef __HAVE_FAST_SOFTINTS
- /* software interrupt */
- ipending &= MIPS_SOFT_INT_MASK;
- if (ipending == 0)
- return;
- softint_process(ipending);
-#endif
-}
+ if (pending & MIPS_INT_MASK_2) {
+ /* tulip secondary */
+ intr_handle(&cpu_intrtab[2]);
+ }
-static const int ipl2spl_table[] = {
- [IPL_NONE] = 0,
- [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1,
- [IPL_VM] = SPLVM,
- [IPL_SCHED] = SPLSCHED,
-};
-
-ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._spl = ipl2spl_table[ipl]};
+ if (pending & MIPS_INT_MASK_4) {
+ /* ICU interrupts */
+ intr_handle(&cpu_intrtab[4]);
+ }
+ (void)splhigh();
+ }
}
Index: src/sys/arch/cobalt/cobalt/machdep.c
diff -u src/sys/arch/cobalt/cobalt/machdep.c:1.98.10.2 src/sys/arch/cobalt/cobalt/machdep.c:1.98.10.3
--- src/sys/arch/cobalt/cobalt/machdep.c:1.98.10.2 Mon Feb 1 04:17:50 2010
+++ src/sys/arch/cobalt/cobalt/machdep.c Sun Feb 28 04:04:46 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.98.10.2 2010/02/01 04:17:50 matt Exp $ */
+/* $NetBSD: machdep.c,v 1.98.10.3 2010/02/28 04:04:46 matt Exp $ */
/*-
* Copyright (c) 2006 Izumi Tsutsui. All rights reserved.
@@ -50,7 +50,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.98.10.2 2010/02/01 04:17:50 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.98.10.3 2010/02/28 04:04:46 matt Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -125,7 +125,7 @@
phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
int mem_cluster_cnt;
-void mach_init(unsigned int, u_int, char*);
+void mach_init(uint32_t, u_int, uint32_t);
void decode_bootstring(void);
static char *strtok_light(char *, const char);
static u_int read_board_id(void);
@@ -145,9 +145,11 @@
* Do all the stuff that locore normally does before calling main().
*/
void
-mach_init(unsigned int memsize, u_int bim, char *bip)
+mach_init(uint32_t memsize32, u_int bim, uint32_t bip32)
{
+ intptr_t memsize = (int32_t)memsize32;
char *kernend;
+ char *bip = (char *)(intptr_t)(int32_t)bip32;
u_long first, last;
extern char edata[], end[];
const char *bi_msg;
@@ -185,14 +187,6 @@
*/
memset(edata, 0, kernend - edata);
- /*
- * XXX
- * lwp0 and cpu_info_store are allocated in BSS
- * and initialized before mach_init() is called,
- * so restore them again.
- */
- lwp0.l_cpu = &cpu_info_store;
- cpu_info_store.ci_curlwp = &lwp0;
}
/* Check for valid bootinfo passed from bootstrap */
@@ -214,8 +208,8 @@
/* Load symbol table if present */
if (bi_syms != NULL) {
nsym = bi_syms->nsym;
- ssym = (void *)bi_syms->ssym;
- esym = (void *)bi_syms->esym;
+ ssym = (void *)(intptr_t)bi_syms->ssym;
+ esym = (void *)(intptr_t)bi_syms->esym;
kernend = (void *)mips_round_page(esym);
}
#endif
@@ -510,12 +504,12 @@
do {
bt = (struct btinfo_common *)help;
- printf("Type %d @0x%x\n", bt->type, (u_int)bt);
+ printf("Type %d @0x%x\n", bt->type, (u_int)(uintptr_t)bt);
if (bt->type == type)
return (void *)help;
help += bt->next;
} while (bt->next != 0 &&
- (size_t)help < (size_t)bootinfo + BOOTINFO_SIZE);
+ (uintptr_t)help < (uintptr_t)bootinfo + BOOTINFO_SIZE);
return NULL;
}
Index: src/sys/arch/cobalt/conf/GENERIC
diff -u src/sys/arch/cobalt/conf/GENERIC:1.119 src/sys/arch/cobalt/conf/GENERIC:1.119.6.1
--- src/sys/arch/cobalt/conf/GENERIC:1.119 Thu Oct 30 16:27:15 2008
+++ src/sys/arch/cobalt/conf/GENERIC Sun Feb 28 04:04:46 2010
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.119 2008/10/30 16:27:15 tsutsui Exp $
+# $NetBSD: GENERIC,v 1.119.6.1 2010/02/28 04:04:46 matt Exp $
#
# GENERIC machine description file
#
@@ -22,7 +22,7 @@
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "GENERIC-$Revision: 1.119 $"
+#ident "GENERIC-$Revision: 1.119.6.1 $"
maxusers 32
@@ -50,7 +50,7 @@
options DDB # kernel dynamic debugger
#options DDB_HISTORY_SIZE=100 # enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
-makeoptions CPUFLAGS="-march=vr5000 -mabi=32"
+makeoptions CPUFLAGS="-march=vr5000"
# Compatibility options
options COMPAT_43 # compatibility with 4.3BSD binaries
Index: src/sys/arch/cobalt/conf/std.cobalt
diff -u src/sys/arch/cobalt/conf/std.cobalt:1.13 src/sys/arch/cobalt/conf/std.cobalt:1.13.80.1
--- src/sys/arch/cobalt/conf/std.cobalt:1.13 Tue Jul 18 12:51:01 2006
+++ src/sys/arch/cobalt/conf/std.cobalt Sun Feb 28 04:04:46 2010
@@ -1,8 +1,7 @@
-# $NetBSD: std.cobalt,v 1.13 2006/07/18 12:51:01 tsutsui Exp $
+# $NetBSD: std.cobalt,v 1.13.80.1 2010/02/28 04:04:46 matt Exp $
machine cobalt mips
include "conf/std" # MI standard options
-makeoptions MACHINE_ARCH="mipsel"
options MIPS3
options MIPS3_ENABLE_CLOCK_INTR
Index: src/sys/arch/cobalt/include/intr.h
diff -u src/sys/arch/cobalt/include/intr.h:1.32.12.1 src/sys/arch/cobalt/include/intr.h:1.32.12.2
--- src/sys/arch/cobalt/include/intr.h:1.32.12.1 Sat Feb 6 02:57:43 2010
+++ src/sys/arch/cobalt/include/intr.h Sun Feb 28 04:04:46 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.32.12.1 2010/02/06 02:57:43 matt Exp $ */
+/* $NetBSD: intr.h,v 1.32.12.2 2010/02/28 04:04:46 matt Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@@ -28,58 +28,13 @@
#ifndef _COBALT_INTR_H_
#define _COBALT_INTR_H_
-#define IPL_NONE 0 /* Disable only this interrupt. */
-#define IPL_SOFTCLOCK 1 /* generic software interrupts */
-#define IPL_SOFTBIO 1 /* clock software interrupts */
-#define IPL_SOFTNET 2 /* network software interrupts */
-#define IPL_SOFTSERIAL 2 /* serial software interrupts */
-#define IPL_VM 3 /* Memory allocation */
-#define IPL_SCHED 4 /* Disable clock interrupts. */
-#define IPL_HIGH 4 /* Disable all interrupts. */
-#define NIPL 5
-
-/* Interrupt sharing types. */
-#define IST_NONE 0 /* none */
-#define IST_PULSE 1 /* pulsed */
-#define IST_EDGE 2 /* edge-triggered */
-#define IST_LEVEL 3 /* level-triggered */
+#include <mips/intr.h>
#ifdef _KERNEL
#ifndef _LOCORE
#include <sys/evcnt.h>
#include <mips/cpuregs.h>
-#include <mips/locore.h>
-
-#define SPLVM (MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | \
- MIPS_INT_MASK_1 | MIPS_INT_MASK_2 | \
- MIPS_INT_MASK_3 | MIPS_INT_MASK_4)
-#define SPLSCHED (SPLVM | MIPS_INT_MASK_5)
-
-#define spl0() (void)_spllower(0)
-#define splx(s) (void)_splset(s)
-#define splvm() _splraise(SPLVM)
-#define splsched() _splraise(SPLSCHED)
-#define splhigh() _splraise(MIPS_INT_MASK)
-
-#define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0)
-#define splsoftbio() _splraise(MIPS_SOFT_INT_MASK_0)
-#define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
-#define splsoftserial() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
-
-typedef int ipl_t;
-typedef struct {
- int _spl;
-} ipl_cookie_t;
-
-ipl_cookie_t makeiplcookie(ipl_t);
-
-static inline int
-splraiseipl(ipl_cookie_t icookie)
-{
-
- return _splraise(icookie._spl);
-}
#define NCPU_INT 6
#define NICU_INT 16
Added files:
Index: src/sys/arch/cobalt/conf/GENERIC64
diff -u /dev/null src/sys/arch/cobalt/conf/GENERIC64:1.1.4.2
--- /dev/null Sun Feb 28 04:04:46 2010
+++ src/sys/arch/cobalt/conf/GENERIC64 Sun Feb 28 04:04:46 2010
@@ -0,0 +1,10 @@
+# $NetBSD: GENERIC64,v 1.1.4.2 2010/02/28 04:04:46 matt Exp $
+#
+include "arch/cobalt/conf/GENERIC"
+
+makeoptions LP64="yes"
+
+options EXEC_ELF64
+options COMPAT_NETBSD32
+
+#options UVMHIST, UVMHIST_PRINT
Index: src/sys/arch/cobalt/include/netbsd32_machdep.h
diff -u /dev/null src/sys/arch/cobalt/include/netbsd32_machdep.h:1.1.4.2
--- /dev/null Sun Feb 28 04:04:46 2010
+++ src/sys/arch/cobalt/include/netbsd32_machdep.h Sun Feb 28 04:04:46 2010
@@ -0,0 +1,3 @@
+/* $NetBSD: netbsd32_machdep.h,v 1.1.4.2 2010/02/28 04:04:46 matt Exp $ */
+
+#include <mips/netbsd32_machdep.h>
