Re: [PATCH 0/4] Virtualize architectural LBRs

ain what needs doing, > and in roughly which order. I would appreciate explanations of the pending XSS issues. Ngoc Tu Dinh | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech

Re: [PATCH 0/4] Virtualize architectural LBRs

On 18/11/2024 09:52, Jan Beulich wrote: > Looking over just the files touched: No change to XSAVE logic at all? XSAVE is hidden behind a new IA32_XSS bit. I'll try to implement that next. Ngoc Tu Dinh | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech

Re: [PATCH 0/4] Virtualize architectural LBRs

Hi Andrew, On 18/11/2024 10:52, Andrew Cooper wrote: > On 18/11/2024 9:13 am, Tu Dinh wrote: >> On 18/11/2024 09:52, Jan Beulich wrote: >>> Looking over just the files touched: No change to XSAVE logic at all? >> XSAVE is hidden behind a new IA32_XSS bit. I'll try to

[RFC PATCH v2 01/10] x86: Add architectural LBR definitions

Signed-off-by: Tu Dinh --- xen/arch/x86/include/asm/msr-index.h | 12 1 file changed, 12 insertions(+) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 9cdb5b2625..97df740b04 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen

[RFC PATCH v2 09/10] x86/vmx: Implement arch LBR

Use guest LBR_CTL in VMCS to limit LBR operation per guest. Use MSR bitmap to disable interception of arch LBR MSRs. Reconfigure bitmap on each valid LBR depth write. Signed-off-by: Tu Dinh --- xen/arch/x86/domain.c | 7 + xen/arch/x86/hvm/vmx/vmcs.c | 11

[RFC PATCH v2 02/10] x86: Define arch LBR feature bits

Add three featureset words corresponding to the 3 CPUID words in leaf 0x1c. Intel SDM states that CPUID may indicate a LBR depth of up to 64. However, since XSAVE LBR state only goes up to 32 LBRs, don't expose the other CPUID depth bits for now. Signed-off-by: Tu Dinh --- xen/arch/x86/in

[RFC PATCH v2 00/10] Virtualize architectural LBRs

by adding a new HVM save code CPU_XSAVES_CODE containing a vCPU's compacted xstates as written by XSAVES. I'm looking for feedback on emulator handling of XSAVES/XRSTORS, especially concerning FPU bits as it's not clear to me what should be done in these cases. Tu Dinh (10): x86: Ad

[RFC PATCH v2 03/10] tools: Add arch LBR feature bits

Signed-off-by: Tu Dinh --- tools/libs/light/libxl_cpuid.c | 3 +++ tools/misc/xen-cpuid.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c index 063fe86eb7..05be36f258 100644 --- a/tools/libs/light/libxl_cpuid.c +++ b

[RFC PATCH v2 06/10] x86: Enable XSTATE save/restore for arch LBR

Add a function get_xstate_component_comp() to allow fetching a specific XSTATE component from a compressed image. Also add LBR state declarations in xstate.h. Signed-off-by: Tu Dinh --- xen/arch/x86/include/asm/xstate.h | 22 - xen/arch/x86/msr.c| 3 +- xen/arch/x86

[RFC PATCH v2 08/10] x86/emulate: Implement XSAVES/XRSTORS for arch LBR

Add new set_lbr_depth HVM function and emulate ops to support LBR XSAVES/XRSTORS emulation. Add the appropriate instruction hooks to 0fc7.c. Translate LBR registers using cs.base within a large block emulator operation. Signed-off-by: Tu Dinh --- tools/tests/x86_emulator/x86-emulate.h | 2

[RFC PATCH v2 10/10] x86/hvm: Enable XSAVES LBR save/restore

Add a new save code type CPU_XSAVES_CODE containing a compressed XSAVES image. Signed-off-by: Tu Dinh --- xen/arch/x86/hvm/hvm.c | 67 +- xen/arch/x86/xstate.c | 3 +- xen/include/public/arch-x86/hvm/save.h | 4 +- 3 files changed, 60

[RFC PATCH v2 04/10] x86: Calculate arch LBR CPUID policies

Ensure that the arch LBR feature and its dependents are disabled if any prerequisites are not available. Signed-off-by: Tu Dinh --- xen/arch/x86/cpu-policy.c | 28 xen/arch/x86/cpu/common.c | 7 +++ 2 files changed, 35 insertions(+) diff --git a/xen/arch/x86

[RFC PATCH v2 05/10] x86: Keep a copy of XSAVE area size

Signed-off-by: Tu Dinh --- xen/arch/x86/include/asm/domain.h | 1 + xen/arch/x86/xstate.c | 1 + 2 files changed, 2 insertions(+) diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index b79d6badd7..d3f2695c20 100644 --- a/xen/arch/x86/include/asm

[RFC PATCH v2 07/10] x86/hvm: Don't count XSS bits in XSAVE size

HVM vCPU state images are uncompressed and therefore can't contain XSS states. Signed-off-by: Tu Dinh --- xen/arch/x86/hvm/hvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 922c9b3af6..c7b93c7d91 100644 ---

[PATCH 3/4] x86: Adjust arch LBR CPU policy

From: Tu Dinh Allow virtual arch LBR with a single depth that's equal to that of the host. If this is not possible, disable arch LBR altogether. Signed-off-by: Tu Dinh --- xen/arch/x86/cpu-policy.c | 33 + 1 file changed, 33 insertions(+) diff --git a/xen

[PATCH 2/4] x86: Add architectural LBR declarations

From: Tu Dinh Signed-off-by: Tu Dinh --- xen/arch/x86/include/asm/msr-index.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 9cdb5b2625..867deab3c6 100644 --- a/xen/arch/x86/include/asm/msr

[PATCH 4/4] x86/vmx: Virtualize architectural LBRs

From: Tu Dinh Virtual architectural LBRs work in guest mode only, using the "load guest IA32_LBR_CTL" and "clear IA32_LBR_CTL" VMX controls. Intercept writes to MSR_IA32_LASTBRANCH_{CTL,DEPTH} to inject LBR MSRs into guest. MSR_IA32_LASTBRANCH_DEPTH is only allowed to be

[PATCH 0/4] Virtualize architectural LBRs

From: Tu Dinh Intel model-specific last branch records (LBRs) were replaced by architectural LBRs (see Chapter 20 of Intel SDM volume 3B). This patchset implements virtual LBRs for HVM guests using Intel's "load guest IA32_LBR_CTL" and "clear IA32_LBR_CTL" VMX controls.

[PATCH 1/4] x86: Add Intel architectural LBR featureset bits

From: Tu Dinh Expose ARCH_LBR feature to guests. Extend CPU featureset with 3 words for CPUID leaf 0x1c. Signed-off-by: Tu Dinh --- tools/libs/guest/xg_cpuid_x86.c | 2 +- tools/misc/xen-cpuid.c | 3 ++ xen/arch/x86/cpu-policy.c | 3

[PATCH 2/2] x86: Set up framebuffer given by Multiboot2

Previously, we do not make use of the framebuffer given by Multiboot. This means graphics will not work in some scenarios such as booting from Kexec. Enable the Multiboot framebuffer if it exists and not overridden by EFI probe. --- xen/arch/x86/setup.c | 45 ++

[PATCH 1/2] x86: Parse Multiboot2 framebuffer information

Multiboot2 exposes framebuffer data in its boot information tags. Xen requests this information from the bootloader, but does not make use of it. Parse this information for later use. --- xen/arch/x86/boot/reloc.c| 22 ++ xen/include/xen/multiboot.h | 17 +

[PATCH 0/2] x86: Use Multiboot framebuffer

Xen does not currently use the Multiboot framebuffer. This means there is no graphics when booting Xen with Kexec. This patchset parses and uses the Multiboot framebuffer information during boot. Tu Dinh Ngoc (2): x86: Parse Multiboot2 framebuffer information x86: Set up framebuffer given by

[PATCH v2] x86: Use low memory size directly from Multiboot

Previously, Xen used information from the BDA to detect the amount of available low memory. This does not work on some scenarios such as Coreboot, or when booting from Kexec on a UEFI system without CSM. Use the information directly supplied by Multiboot boot information instead. --- xen/arch/x86

[PATCH v3] x86: Prioritize low memory size from Multiboot

to the old BDA method. Signed-off-by: Tu Dinh Ngoc --- Changes in v3: - Prioritize using Multiboot's memory information.. Fall back to using BDA in case MBI does not supply memory info. Changes in v2: - Detect if Multiboot claims there's more than 640 KB of low memory (happens with