Instead of just doing it for the BSP. This requires storing the
maximum number of possible vCPUs in xc_dom_image.
This has been a latent bug so far because PVH doesn't yet support
pci-passthrough, so the effective memory cache attribute is forced to
WB by the hypervisor. Note also that even withou
Commit 2916951c1 changed the check in iommu_share_p2m_table to use
need_iommu(d) instead of iommu_enabled, which broke the check because
at the point in domain construction where iommu_share_p2m_table is
called need_iommu(d) will always return false.
Fix this by reverting to the previous logic.
S
Commit 2916951c1 "mm / iommu: include need_iommu() test in
iommu_use_hap_pt()" changed the check in iommu_share_p2m_table to use
need_iommu(d) (as part of iommu_use_hap_pt) instead of iommu_enabled,
which broke the check because at the point in domain construction
where iommu_share_p2m_table is cal
When switching the memory decoding bit in the command register the
rest of the changes where dropped, leading to only the memory decoding
bit being updated.
Fix this by unconditionally writing the guest-requested command except
for the memory decoding bit, which will be updated once the p2m
change
No functional change expected.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Wei Liu
---
xen/arch/x86/dom0_build.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c
index 86eb7db1da..dc
BAR map/unmap is a long running operation that needs to be preempted
in order to avoid overrunning the assigned vCPU time (or even
triggering the watchdog).
Current logic for this preemption is wrong, and won't work at all for
AMD since only Intel makes use of hvm_io_pending (and even in that
case
A PVH Dom0 might use TSC scaling or other HVM specific TSC
adjustments, so only short-circuit the TSC setup for a classic PV
Dom0.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Wei Liu
---
xen/arch/x86/time.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Make sure the MSIX MMIO regions don't have p2m entries setup, so that
accesses to them trap into the hypervisor and can be handled by vpci.
This is a side-effect of commit 042678762 for PVH Dom0, which added
mappings for all the reserved regions into the Dom0 p2m.
Signed-off-by: Roger Pau Monné
Add an option to allow trapping accesses to IO port 0xe9 for a PVH
Dom0, so it can print to the HVM debug console. Note this is not
enabled by default in order to prevent clashes with hardware on the
system using 0xe9.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Wei
Thanks, Roger.
Roger Pau Monne (6):
x86/pvh: fix TSC mode setup for PVH Dom0
x86/dom0: switch parse_dom0_param to use parse_boolean
x86/pvh: allow PVH Dom0 to use the debug IO port console
vpci: fix updating the command register
vpci: fix execution of long running operations
vpci/
While booting on an AMD EPYC box the stack canary would detect stack
overflows when using the current PVH early stack size (256). Switch to
using the value defined by BOOT_STACK_SIZE, which prevents the stack
overflow.
Signed-off-by: Roger Pau Monné
---
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc:
Instead of just doing it for the BSP. This requires storing the
maximum number of possible vCPUs in xc_dom_image.
This has been a latent bug so far because PVH doesn't yet support
pci-passthrough, so the effective memory cache attribute is forced to
WB by the hypervisor. Note also that even withou
A PVH Dom0 might use TSC scaling or other HVM specific TSC
adjustments, so only short-circuit the TSC setup for a classic PV
Dom0.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Wei Liu
---
xen/arch/x86/time.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
When switching the memory decoding bit in the command register the
rest of the changes where dropped, leading to only the memory decoding
bit being updated.
Fix this by unconditionally writing the guest-requested command except
for the memory decoding bit, which will be updated once the p2m
change
PV Dom0 has a quirk for some AMD processors, where enabling ACPI can
also enable C1E mode. Apply the same workaround as done on PV for a
PVH Dom0, which consist on trapping accesses to the SMI command IO
port and disabling C1E if ACPI is enabled.
Reported-by: Jan Beulich
Signed-off-by: Roger Pau
Make sure the MSIX MMIO regions don't have p2m entries setup, so that
accesses to them trap into the hypervisor and can be handled by vpci.
This is a side-effect of commit 042678762 for PVH Dom0, which added
mappings for all the reserved regions into the Dom0 p2m.
Signed-off-by: Roger Pau Monné
BAR map/unmap is a long running operation that needs to be preempted
in order to avoid overrunning the assigned vCPU time (or even
triggering the watchdog).
Current logic for this preemption is wrong, and won't work at all for
AMD since only Intel makes use of hvm_io_pending (and even in that
case
Add an option to allow trapping accesses to IO port 0xe9 for a PVH
Dom0, so it can print to the HVM debug console. Note this is not
enabled by default in order to prevent clashes with hardware on the
system using 0xe9.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Wei
Hello,
The following series contain miscellaneous fixes for a PVH Dom0. I've
found out this issues while trying to boot on an AMD EPYC box.
The series can be found on my git repo:
git://xenbits.xen.org/people/royger/xen.git fixes-pvh-v2
Thanks, Roger.
Roger Pau Monne (7):
x86/pvh: fi
No functional change intended.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Wei Liu
Cc: George Dunlap
Cc: Ian Jackson
Cc: Julien Grall
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabellini
Cc: Tim Deegan
---
xen/arch/x86/hvm/hvm.c| 4 ++--
xen/drivers/
ang's integrated assembler. Fully compiling Xen with clang's
integrated assembler will require clang 4.0 or newer.
This series has been tested with clang 3.5, clang 6.0 and gcc 6.4.0.
Thanks, Roger.
Roger Pau Monne (5):
build: filter out command line assembler arguments
x86/clang:
If the assembler is not used. This happens when using cc -E or cc -S
for example. GCC will just ignore the -Wa,... when the assembler is
not called, but clang will complain loudly and fail.
This is a preparatory change in order to pass assembler arguments when
using clang.
Signed-off-by: Roger Pa
When indirect_thunk_asm.h is instantiated directly into assembly files
CONFIG_INDIRECT_THUNK might not be defined, and thus using .if against
it is wrong.
Add a check to define CONFIG_INDIRECT_THUNK to 0 if not defined, so
that using .if CONFIG_INDIRECT_THUNK is always correct.
This suppresses th
The build with clang is currently broken because clang integrated
assembler requires asm macros to be declared inside the same inline
asm declaration where they are used.
In order to fix this always include indirect_thunk_asm.h in the same
asm declaration where it's being used.
This has been repo
This makes the code cleaner because there's no need to declare the
exception_table in assembly, and also fixes the following error when
using clang's integrated assembler:
entry.S:834:15: error: unexpected token in '.rept' directive
.rept 32 - ((. - exception_table) / 8)
^
en
Clang assembler doesn't support using .skip with non-absolute
expressions:
entry.S:109:15: error: expected absolute expression
.skip .Lcr4_alt_end - .Lcr4_alt, 0x90
^
This usage of .skip was to fill code sections with NOPs in order for
them to be patched at run time if requi
So it can be used by both gcc and clang. Just add the Kconfig option
and modify the makefiles so the llvm coverage specific code can be
added in a follow up patch.
Signed-off-by: Roger Pau Monné
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
physmap.
Thanks, Roger.
Roger Pau Monne (3):
pvh/dom0: init variables at declaration time
pvh/dom0: pass address/length to pvh_acpi_table_allowed
pvh/dom0: whitelist PVH Dom0 ACPI tables
xen/arch/x86/hvm/dom0_build.c | 75 +--
1 file changed, 37
The current usage of acpi_gbl_root_table_list inside the function is
wrong.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
---
xen/arch/x86/hvm/dom0_build.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/xen/arch/x86/hv
Also remove a couple of newlines at the start of function
declarations.
No functional change.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
---
xen/arch/x86/hvm/dom0_build.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/xen/arch/
Signed-off-by: Roger Pau Monné
---
xen/arch/x86/hvm/dom0_build.c | 31 ++-
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_build.c
index 830b4345cc..82ee3fe237 100644
--- a/xen/arch/x86/hvm/dom0_buil
There a bunch of bits in CR4 that should be allowed to be set directly
by the guest without requiring Xen intervention, currently this is
already done by passing through guest writes into the CR4 used when
running in non-root mode, but taking an expensive vmexit in order to
do so.
xenalyze reports
The new shim tests uses the same approach as the PVH one, but doesn't
differentiate between AMD and Intel.
This is the (trimmed) diff of the output from mg-show-flight-runvars:
+test-amd64-amd64-xl-pvshimall_host_di_version2017-12-14
+test-amd64-i386-xl-pvshim all_host_di_version2
later.
Thanks, Roger.
Roger Pau Monne (2):
x86/hvm: introduce cr_mask to store trapped bits of CR accesses
vmx/hap: optimize CR4 trapping
xen/arch/x86/hvm/svm/vmcb.c| 1 +
xen/arch/x86/hvm/vmx/vmcs.c| 1 +
xen/arch/x86/hvm/vmx/vmx.c | 39 +++
xen
At the moment this is currently set at VMCS creation and not changed,
but further patches are going to change the CR4 mask at runtime.
Signed-off-by: Roger Pau Monné
---
Cc: Boris Ostrovsky
Cc: Suravee Suthikulpanit
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Jun Nakajima
Cc: Kevin Tian
---
Chang
There a bunch of bits in CR4 that should be allowed to be set directly
by the guest without requiring Xen intervention, currently this is
already done by passing through guest writes into the CR4 used when
running in non-root mode, but taking an expensive vmexit in order to
do so.
xenalyze reports
Previous usage is not correct and would prevent certain updates from
being notified to the monitor client.
For example if (value ^ old) == (PGE | PSE) and mask == PGE this
update would not be notified.
Signed-off-by: Roger Pau Monné
---
Cc: Razvan Cojocaru
Cc: Tamas K Lengyel
Cc: Jan Beulich
When indirect_thunk_asm.h is instantiated directly into assembly files
CONFIG_INDIRECT_THUNK might not be defined, and thus using .if against
it is wrong.
Add a check to define CONFIG_INDIRECT_THUNK to 0 if not defined, so
that using .if CONFIG_INDIRECT_THUNK is always correct.
This suppresses th
the usage of -no-integrated-as from AFLAGS when
possible.
This series has been tested with clang 6 (without -no-integrated-as),
clang 3.5 and gcc 6.
Thanks, Roger.
Roger Pau Monne (4):
build: filter out command line assembler arguments
x86/clang: restore integrated assembler usage with
If the assembler is not used. This happens when using cc -E or cc -S
for example. GCC will just ignore the -Wa,... when the assembler is
not called, but clang will complain loudly and fail.
Also enable passing -Wa,-I$(BASEDIR)/include to clang now that it's
safe to do so.
Signed-off-by: Roger Pau
Or else switch off the integrated assembler. This is relevant for
older clang versions which integrated assembler don't support .skip
with labels.
Signed-off-by: Roger Pau Monné
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stab
If the required features are meet by the integrated clang assembler
(support for .includes and propagation of .macro-s between asm()-s)
do not disable it.
Only switch off the non integrated assembler for assembly file, like
it was done prior to "x86: Support indirect thunks from assembly
code".
S
There's no need to have shim specific targets, so just use the regular
xen makefile targets in order to build the shim binary.
When the shim is build as part of the firmware directory use the
xen-syms as the shim binary.
Signed-off-by: Roger Pau Monné
---
Cc: Ian Jackson
Cc: Wei Liu
Cc: Andrew
There a bunch of bits in CR4 that should be allowed to be set directly
by the guest without requiring Xen intervention, currently this is
already done by passing through guest writes into the CR4 used when
running in non-root mode, but taking an expensive vmexit in order to
do so.
xenalyze reports
At the moment this is currently set at VMC{S/B} creation and not changed,
but further patches are going to change the CR4 mask at runtime.
Signed-off-by: Roger Pau Monné
---
Cc: Boris Ostrovsky
Cc: Suravee Suthikulpanit
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Jun Nakajima
Cc: Kevin Tian
---
C
later.
Thanks, Roger.
Roger Pau Monne (2):
x86/hvm: introduce cr{0,4}_host_mask to store trapped bits of CR
accesses
vmx/hap: optimize CR4 trapping
xen/arch/x86/hvm/svm/vmcb.c| 1 +
xen/arch/x86/hvm/vmx/vmcs.c| 1 +
xen/arch/x86/hvm/vmx/vmx.c
If the required features are met by the integrated clang assembler
(support for .includes and propagation of .macro-s between asm()-s)
do not disable it.
Only disable the integrated assembler for assembly files, like it was
done prior to "x86: Support indirect thunks from assembly code".
Signed-o
When indirect_thunk_asm.h is instantiated directly into assembly files
CONFIG_INDIRECT_THUNK might not be defined, and thus using .if against
it is wrong.
Add a check to define CONFIG_INDIRECT_THUNK to 0 if not defined, so
that using .if CONFIG_INDIRECT_THUNK is always correct.
This suppresses th
Or else disable the integrated assembler for assembly files. This is
relevant for older clang versions which integrated assembler don't
support .skip with labels.
Signed-off-by: Roger Pau Monné
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
If the assembler is not used. This happens when using cc -E or cc -S
for example. GCC will just ignore the -Wa,... when the assembler is
not called, but clang will complain loudly and fail.
Also enable passing -Wa,-I$(BASEDIR)/include to clang now that it's
safe to do so.
Signed-off-by: Roger Pau
Hardcoding as-insn to use AFLAGS is not correct. For once the test is
performed using a C file with inline assembly, and secondly the flags
used can be passed by the caller together with the CC.
Fix as-insn-check to pass the flags given as parameter to the test.
Signed-off-by: Roger Pau Monné
--
Hello,
The following series re-enable the integrated clang assembler when the
features required in order to build Xen are available.
This series has been tested with clang 6, clang 3.5, gcc 6 and gcc 7
with indirect branch support.
Thanks, Roger.
Roger Pau Monne (5):
build: do not hardcode
There's no need to have shim specific targets, so just use the regular
xen makefile targets in order to build the shim binary.
When the shim is build as part of the firmware directory install the
stripped Xen binary to the firmware directory and place a binary with
symbols in the debug directory.
There's no need to have shim specific targets, so just use the regular
xen makefile targets in order to build the shim binary.
When the shim is build as part of the firmware directory install the
stripped Xen binary to the firmware directory and place a binary with
symbols in the debug directory.
On FreeBSD the build fails with:
/root/src/xtf/include/xtf/compiler.h:13:9: error: '__section' macro redefined
[-Werror,-Wmacro-redefined]
#define __section(s) __attribute__((__section__(s)))
^
/usr/include/sys/cdefs.h:229:9: note: previous definition is here
#define __secti
Execute periodic_time callbacks even if the interrupt is not actually
injected because the IRQ is masked.
Current callbacks from emulated timer devices only update emulated
registers, which from my reading of the specs should happen regardless
of whether the interrupt has been injected or not.
Si
Hello,
This series add support for level triggered HPET interrupts, which are
mandatory according to the spec.
First patch is a change for vpt in order to execute the timer
callbacks even if the interrupt is not injected because the IRQ is
masked. Second patch implements support for level trigger
Level triggered interrupts are not an optional feature of HPET, and
must be implemented in order to comply with the HPET specification.
Implement them by adding a callback to the timer which sets the
interrupt bit in the general interrupt status register. Further
interrupts (in case of periodic mo
Add a basic HPET functionality test, note that this test requires the
HPET to support level triggered interrupts.
Further improvements should add support for interrupt delivery, and
testing all the available timers.
Signed-off-by: Roger Pau Monné
---
Cc: Andrew Cooper
---
arch/x86/include/arch
If the required features are present.
Modify as-option-add to add an option in case the test fails, and use
it to detect whether the required clang integrated assembler features
are present.
This patch has been tested with clang 3.5, clang 6, gcc 6.4.0 without
retpoline support and gcc 7.3.1 with
There a bunch of bits in CR4 that should be allowed to be set directly
by the guest without requiring Xen intervention, currently this is
already done by passing through guest writes into the CR4 used when
running in non-root mode, but taking an expensive vmexit in order to
do so.
xenalyze reports
Current cleanup in the error path of xen_bind_pirq_msi_to_irq is
wrong. First of all there's an off-by-one in the cleanup loop, which
can lead to unbinding wrong IRQs.
Secondly IRQs not bound won't be freed, thus leaking IRQ numbers.
Note that there's no need to differentiate between bound and un
XSA-256 forces the local APIC to always be enabled for PVH guests, so
ignore any apic option for PVH guests. Update the documentation
accordingly.
Signed-off-by: Roger Pau Monné
---
Cc: Ian Jackson
Cc: Wei Liu
---
docs/man/xl.cfg.pod.5.in | 6 --
tools/libxl/libxl_x86.c | 6 +-
tools/
To add the shim build output and build directory.
Signed-off-by: Roger Pau Monné
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabellini
Cc: Tim Deegan
Cc: Wei Liu
---
.hgignore | 5 +
1 file changed, 5 insertions(+)
d
Add the shim build symbol file and remove the xen-shim binary (which
is no longer created).
Reported-by: Olaf Hering
Signed-off-by: Roger Pau Monné
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabellini
Cc: Tim Deegan
Cc: W
Commit 406817 doesn't update nested VMX code in order to take into
account L1 CR4 host mask when nested guest (L2) writes to CR4, and
thus the mask written to CR4_GUEST_HOST_MASK is likely not as
restrictive as it should be.
Also the VVMCS GUEST_CR4 value should be updated to match the
underlying
Commit 406817 doesn't update nested VMX code in order to take into
account L1 CR4 host mask when nested guest (L2) writes to CR4, and
thus the mask written to CR4_GUEST_HOST_MASK is likely not as
restrictive as it should be.
Also the VVMCS GUEST_CR4 value should be updated to match the
underlying
Force trapping accesses to IO port 0xe9 for a PVH Dom0, so it can
print to the HVM debug console.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Wei Liu
---
Changes since v2:
- Always enable the E9 debug console.
Changes since v1:
- Use a define for 0xe9.
- Expand
BAR map/unmap is a long running operation that needs to be preempted
in order to avoid overrunning the assigned vCPU time (or even
triggering the watchdog).
Current logic for this preemption is wrong, and won't work at all for
AMD since only Intel makes use of hvm_io_pending (and even in that
case
No functional change intended.
Signed-off-by: Roger Pau Monné
Reviewed-by: Jan Beulich
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Wei Liu
Cc: George Dunlap
Cc: Ian Jackson
Cc: Julien Grall
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabellini
Cc: Tim Deegan
---
xen/arch/x86/hvm/hvm.c
Hello,
The following series contain miscellaneous fixes for a PVH Dom0. I've
found out this issues while trying to boot on an AMD EPYC box.
The series can be found on my git repo:
git://xenbits.xen.org/people/royger/xen.git fixes-pvh-v3
Roger Pau Monne (7):
x86/pvh: fix TSC mode setu
A PVH Dom0 might use TSC scaling or other HVM specific TSC
adjustments, so only short-circuit the TSC setup for a classic PV
Dom0.
Signed-off-by: Roger Pau Monné
Acked-by: Jan Beulich
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Wei Liu
---
xen/arch/x86/time.c | 2 +-
1 file changed, 1 insertio
PV Dom0 has a quirk for some AMD processors, where enabling ACPI can
also enable C1E mode. Apply the same workaround as done on PV for a
PVH Dom0, which consist on trapping accesses to the SMI command IO
port and disabling C1E if ACPI is enabled.
Reported-by: Jan Beulich
Signed-off-by: Roger Pau
When switching the memory decoding bit in the command register the
rest of the changes where dropped, leading to only the memory decoding
bit being updated.
Fix this by unconditionally writing the guest-requested command except
for the memory decoding bit, which will be updated once the p2m
change
Make sure the MSIX MMIO regions don't have p2m entries setup, so that
accesses to them trap into the hypervisor and can be handled by vpci.
This is a side-effect of commit 042678762 for PVH Dom0, which added
mappings for all the reserved regions into the Dom0 p2m.
Signed-off-by: Roger Pau Monné
PV Dom0 has a quirk for some AMD processors, where enabling ACPI can
also enable C1E mode. Apply the same workaround as done on PV for a
PVH Dom0, which consist on trapping accesses to the SMI command IO
port and disabling C1E if ACPI is enabled.
Reported-by: Jan Beulich
Signed-off-by: Roger Pau
When running as a PVH guest Xen only special cases the trampoline
code in the low 1MB, without also reserving the space used by the
relocated metadata or the trampoline stack.
Fix this by always reserving the low 1MB regardless of whether Xen is
running as a guest or natively.
Reported-by: Sergey
fix_memory_scrub_v1
Roger Pau Monne (2):
guest/pvh: fix handling of multiboot info and module list
guest/pvh: special case the low 1MB
xen/arch/x86/guest/pvh-boot.c| 20 ++--
xen/arch/x86/mm.c| 13 +
xen/arch/x86/setup.c | 7
When booting Xen as a PVH guest the data in the PVH start info
structure is copied over to a multiboot structure and a module list
array that resides in the .init section of the Xen image. The
resulting multiboot structures are then handled to the generic boot
process using their physical address.
When booting Xen as a PVH guest the data in the PVH start info
structure is copied over to a multiboot structure and a module list
array that resides in the .init section of the Xen image. The
resulting multiboot structures are then handled to the generic boot
process using their physical address.
When switching the memory decoding bit in the command register the
rest of the changes where dropped, leading to only the memory decoding
bit being updated.
Fix this by writing the command register once the guest physmap
manipulations are done if there are changes to the memory decoding
bit.
Sign
Current logic to handle long running operations has two flaws:
- hvm_io_pending is only used by Intel code, fix this by moving the
call to vpci_process_pending into handle_hvm_io_completion.
- Raise a scheduler softirq when preemption is required. The
do_softirq calls in the SVM/VMX guest
Hello,
The following series contain miscellaneous fixes for a PVH Dom0. I've
found out this issues while trying to boot on an AMD EPYC box.
The series can be found on my git repo:
git://xenbits.xen.org/people/royger/xen.git fixes-pvh-v4
Roger Pau Monne (5):
vpci: fix updating the co
Make sure the MSIX MMIO regions don't have p2m entries setup, so that
accesses to them trap into the hypervisor and can be handled by vpci.
Commit 042678762 ("x86/iommu: add map-reserved dom0-iommu option to
map reserved memory ranges") added mappings for all the reserved
regions into the PVH Dom0
Bridges are not behind an IOMMU, and are already special cased and
silently skipped in amd_iommu_add_device. Apply the same special
casing when updating page tables.
Signed-off-by: Roger Pau Monné
---
Cc: Suravee Suthikulpanit
Cc: Brian Woods
---
xen/drivers/passthrough/amd/iommu_map.c | 4 +++
AMD IOMMU devices are exposed on the PCI bus, and thus are assigned by
default to the hardware domain. This can cause issues because the
IOMMU devices are not behind an IOMMU, and conceptually it's also wrong
to give the hardware domain ownership of those devices since they are
in use by Xen.
Fix
As I've touched quite a lot of this code in order to add PVH and PV
shim support I would like to keep an eye on incoming changes, and
since I'm also attempting to review patches in this area it's going to
be easier if I get CCed on them.
Signed-off-by: Roger Pau Monné
---
Cc: Andrew Cooper
Cc: G
Current logic to handle long running operations is flawed because it
doesn't prevent the guest vcpu from running. Fix this by raising a
scheduler softirq when preemption is required, so that the do_softirq
call in the guest entry path performs a rescheduling. Also move the
call to vpci_process_pend
No functional change expected.
Signed-off-by: Roger Pau Monné
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Julien Grall
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabellini
Cc: Tim Deegan
Cc: Wei Liu
---
Changes since v4:
- New in this version.
---
xen/driver
Hello,
The following series contain miscellaneous fixes for a PVH Dom0. I've
found out this issues while trying to boot on an AMD EPYC box.
The series can be found on my git repo:
git://xenbits.xen.org/people/royger/xen.git fixes-pvh-v5
Roger Pau Monne (6):
vpci: fix updating the co
Bridges are not behind an IOMMU, and are already special cased and
skipped in amd_iommu_add_device. Apply the same special casing when
updating page tables.
This is required or else update_paging_mode will fail and return an
error to the caller (amd_iommu_{un}map_page) which will destroy the
domai
Make sure the MSIX MMIO regions don't have p2m entries setup, so that
accesses to them trap into the hypervisor and can be handled by vpci.
Commit 042678762 ("x86/iommu: add map-reserved dom0-iommu option to
map reserved memory ranges") added mappings for all the reserved
regions into the PVH Dom0
AMD IOMMU devices are exposed on the PCI bus, and thus are assigned by
default to the hardware domain. This can cause issues because the
IOMMU devices themselves are not behind an IOMMU, so update_paging_mode will
return an error if Xen tries to expand the page tables of a domain
that has assigned
When switching the memory decoding bit in the command register the
rest of the changes where dropped, leading to only the memory decoding
bit being updated.
Fix this by writing the command register once the guest physmap
manipulations are done if there are changes to the memory decoding
bit.
Note
LLVM code generation can attempt to perform a load from a variable in
the next condition of an expression under certain circumstances, thus
turning the following condition:
if ( system_state < SYS_STATE_active && opt_bootscrub == BOOTSCRUB_IDLE )
Into:
0x82d080223967 <+103>: cmpl $0x3,0x37
LLVM code generation can attempt to load from a variable in the next
condition of an expression under certain circumstances, thus turning
the following condition:
if ( system_state < SYS_STATE_active && opt_bootscrub == BOOTSCRUB_IDLE )
Into:
0x82d080223967 <+103>: cmpl $0x3,0x37b032(%rip)
There's no other way to shutdown a PVH guest at the moment.
Signed-off-by: Roger Pau Monné
---
Cc: Ian Jackson
Cc: Wei Liu
---
tools/libxl/libxl_domain.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/libxl/libxl_domain.c b/tools/libxl/libxl_domain.c
index 814f8128a1
Avoid scheduling vCPUs that are blocked, there's no point in assigning
them to a pCPU because they are not going to run anyway and might
prevent a non-blocked vCPU from actually running.
Signed-off-by: Roger Pau Monné
---
Cc: George Dunlap
Cc: Dario Faggioli
---
xen/common/sched_null.c | 4 +++
The following patches remove two leftovers.
Thanks, Roger.
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Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
---
xen/arch/x86/pv/dom0_build.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c
index a13412efb9..6a5fc326f7 100644
--- a/xen/arch/
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