't think
XEN_DOMCTL_memory_mapping should be able to map reserved-regions. So the
iomem rangeset should not contain them.
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On 08/05/2019 10:25, Andrii Anisov wrote:
Hello Julien,
On 03.05.19 13:19, Julien Grall wrote:
Could you be a bit more specific about the failure? Do you see "Failed to walk
page-table"?
Sorry for a delayed answer.
Yes, I see еру following, also with
2 +
xen/include/xen/sched.h | 8
7 files changed, 227 insertions(+), 48 deletions(-)
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heers,
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y who. Maybe:
union
{
/* Legacy interface to be used when the guest provides a virtual address */
union {
XEN_GUEST_HANDLE(vcpu_runstate_info_t) native;
...
} virt;
/* Interface used when the guest provides a physical address */
union {
} phys;
} runstate_guest.
runstate_guest_type /* could be a bool or enum */
Jan what do you think?
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() to be within the critical region,
and moving the call simplifies the error case.
No practical change in functionaltiy.
s/functionaltiy/functionality/
Signed-off-by: Andrew Cooper
Reviewed-by: Julien Grall
I will fix up the typo and queue it in my next-4.13 branch.
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The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
non-boot CPU. So introduce a function to set the bit and clear TLBs.
This new function will help us to document and update the logic in a
single place.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2
At the moment, create_xen_entries will only flush the TLBs if the full
range has successfully been updated. This may lead to leave unwanted
entries in the TLBs if we fail to update some entries.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2:
- Add
At the moment, TLB helpers are scattered in 2 headers: page.h (for
Xen TLB helpers) and tlbflush.h (for guest TLB helpers).
This patch is gathering all of them in tlbflush. This will help to
uniformize and update the logic of the helpers in follow-up patches.
Signed-off-by: Julien Grall
don't match the implementation.
Lastly, switch from unsigned lont to vaddr_t as the function technically
deal with virtual address.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2:
- Add Andrii's reviewed-by
---
xen/arch/arm/mm.c
() would
who need to invalidate the instruction cache.
So rather than keeping around the function flush_xen_text_tlb_local()
around, replace it with call to flush_xen_tlb_local() and explicitely
flush the cache when necessary.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in
are a lack of documentation in most of the TLBs helper.
Rather than trying to update the helpers one by one, this patch
introduce a per-arch macro to generate the TLB helpers. This will be
easier to update the TLBs helper in the future and the documentation.
Signed-off-by: Julien Grall
Reviewed
part over the next few weeks.
In this first part, I focus on reworking how we flush the TLBs in Xen.
Cheers,
Julien Grall (7):
xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
xen/arm: Remove flush_xen_text_tlb_local()
xen/arm: tlbflush: Clarify the TLB helpers name
xen/arm:
TLB helpers in the headers tlbflush.h are currently quite confusing to
use the name may lead to think they are dealing with hypervisors TLBs
while they actually deal with guest TLBs.
Rename them to make it clearer that we are dealing with guest TLBs.
Signed-off-by: Julien Grall
Reviewed-by
merge them in
staging on the tree is reopened.
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On 08/05/2019 17:30, Oleksandr wrote:
On 08.05.19 19:19, Julien Grall wrote:
Hi Oleksandr,
Hi Julien
On 02/05/2019 18:00, Oleksandr Tyshchenko wrote:
Oleksandr Tyshchenko (4):
xen/arm: drivers: scif: Extend driver to handle other interfaces
xen/arm: drivers: scif: Add support
Hi Stefano,
On 5/9/19 7:01 PM, Stefano Stabellini wrote:
On Tue, 7 May 2019, Julien Grall wrote:
Convert online_page, offline_page and query_page_offline to use
typesafe MFN.
I would like to have a statement in the commit message mentioning the
changes below to mci_action_add_pageoffline and
Hi,
On 5/9/19 7:06 PM, Stefano Stabellini wrote:
On Tue, 7 May 2019, Julien Grall wrote:
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index d1bfc82f57..f1761fe183 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -118,4 +118,12 @@ struct vnuma_info
Hi Stefano,
On 5/9/19 7:16 PM, Stefano Stabellini wrote:
On Thu, 9 May 2019, Julien Grall wrote:
Hi,
On 5/9/19 7:06 PM, Stefano Stabellini wrote:
On Tue, 7 May 2019, Julien Grall wrote:
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index d1bfc82f57..f1761fe183 100644
Hi,
On 09/05/2019 21:03, Stefano Stabellini wrote:
> On Wed, 8 May 2019, Julien Grall wrote:
>> The function flush_xen_text_tlb_local() has been misused and will result
>> to invalidate the instruction cache more than necessary.
>>
>> For instance, there are no need to
Hi,
On 09/05/2019 21:13, Stefano Stabellini wrote:
> On Wed, 8 May 2019, Julien Grall wrote:
>> /* Release all __init and __initdata ranges to be reused */
>> diff --git a/xen/include/asm-arm/arm32/page.h
>> b/xen/include/asm-arm/arm32/page.h
>> index 40a77daa9d..0b4
On 09/05/2019 21:32, Stefano Stabellini wrote:
> On Wed, 8 May 2019, Julien Grall wrote:
> I agree with what you are trying to achieve with this patch and I like
> the idea of reducing code duplication. As I look at the code, I was
> hoping to find a way to avoid introducing ma
Hi,
On 09/05/2019 21:32, Julien Grall wrote:
> Hi,
>
> On 09/05/2019 21:13, Stefano Stabellini wrote:
>> On Wed, 8 May 2019, Julien Grall wrote:
>>> /* Release all __init and __initdata ranges to be reused */
>>> diff --git a/xen/include/asm-arm/arm32/page.h
r
down.
Because __trace_var will export the value to the guest. I wasn't sure whether we
can safely consider that gfn_t is exactly the same as unsigned long in debug-build.
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don't have enough experience with x86 to provide the patch you suggest.
I am happy to rebase on top of any patch you provide. Alternatively I can drop
this and keep mfn_to_gmfn on x86 but replaces the one in common code with
mfn_to_gfn.
Reviewed-by: Jan Beulich
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rror 2
make[1]: Leaving directory '/home/julieng/works/xen/xen'
Makefile:45: recipe for target 'build' failed
make: *** [build] Error 2
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e, what do you think?
I know what's the current definition. My point is we never made that assumption
before. In all honesty, sure assumption would definitely help in a few places,
but I think we ought to safeguard with BUILD_BUG(...).
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e
current split makes sense.
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extern bool machine_to_phys_mapping_valid;
-static inline void set_gpfn_from_mfn(unsigned long mfn, unsigned long pfn)
+static inline void set_pfn_from_mfn(mfn_t mfn, unsigned long pfn)
{
-struct domain *d = page_get_owner(mfn_to_page(_mfn(mfn)));
+const unsigned long mfn_ = mfn_x(mfn);
inal condition (by re-using it verbatim) - I'm pretty
sure this is going to crash.
Good point, I will update the patch.
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ken care of
Reviewed-by: Jan Beulich
Thank you.
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ave a
single header for everything under the same #ifdef...
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f it ever happens, it is easier for a user to grep the code for
the message rather than having to add some to find out where the -EOPNOTSUPP is
coming from.
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faulting non-NULL address, if there is such on Arm.
Patches are welcomed ;).
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his is bogus. The thing is using different format for the MFN
makes it difficult to read a message without looking format string.
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nge 4KB - 2MB) with the rework I am attempting.
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that.
I hope you are aware, this is unlikely going to be printed as the code should
not be called.
ASSERT_UNREACHABLE() then?
And still avoiding the printk?
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fn %"PRI_mfn"
which is almost fully consistent across the x86 code.
If I got it right, the format here would be "wrong owner mfn %"PRI_mfn". Am I
correct?
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ALID_M2P(gmfn) )
-shadow_remove_all_shadows(owner, _mfn(gmfn));
+shadow_remove_all_shadows(owner, page_to_mfn(page));
}
if ( !(type & PGT_partial) )
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u code the assertion.
If you follow the if()-ASSERT_UNREACHABLE()-return style we've
been using elsewhere, then no matter how you place the #else
or #endif the printk() will be compiled out.
I will have a look.
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On 09/05/2019 22:46, Julien Grall wrote:
Hi,
On 09/05/2019 21:32, Julien Grall wrote:
Hi,
On 09/05/2019 21:13, Stefano Stabellini wrote:
On Wed, 8 May 2019, Julien Grall wrote:
/* Release all __init and __initdata ranges to be reused */
diff --git a/xen/include/asm-arm/arm32/page.h
b/xen
he rework I am attempting.
Hmm, I was hoping for an architecturally faulting address, like
the non-canonical ones we have on x86-64.
Nothing we can reliably use across Armv7 and Armv8 (and future extension).
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On 10/05/2019 16:29, Oleksandr wrote:
Hello, all
gentle reminder...
This is on my long queue of patches to review. Any help reviewing the on-going
series will help.
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Hi,
On 10/05/2019 18:57, Stefano Stabellini wrote:
> On Fri, 10 May 2019, Julien Grall wrote:
>> On 09/05/2019 22:46, Julien Grall wrote:
>>> Hi,
>>>
>>> On 09/05/2019 21:32, Julien Grall wrote:
>>>> Hi,
>>>>
>>>> On 09/0
Hi,
On 10/05/2019 21:51, Stefano Stabellini wrote:
> On Tue, 7 May 2019, Julien Grall wrote:
>> Hi Stefano,
>>
>> On 4/30/19 10:02 PM, Stefano Stabellini wrote:
>>> Reserved memory regions are automatically remapped to dom0. Their device
>>> tree nodes are
On 5/10/19 10:43 PM, Julien Grall wrote:
Hi,
On 10/05/2019 21:51, Stefano Stabellini wrote:
On Tue, 7 May 2019, Julien Grall wrote:
Hi Stefano,
On 4/30/19 10:02 PM, Stefano Stabellini wrote:
Reserved memory regions are automatically remapped to dom0. Their
device
tree nodes are also added
. Are you certain this is my patch and not another error
in Xen 4.12 (or any patch you have on top)?
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frametable_size < MB(32) ? MB(2) :
MB(32);
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irst 1<
I thought I already pointed out in the previous version. At least on
Arm, we never map the first 1 << MAX_ORDER of RAM. Instead what you want
to say is that we don't compress the first N bits of the address.
+ * are left uncompressed.
+ */
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What is require on the make command line?
As usual, patches are welcomed ;).
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Hi,
On 5/8/19 5:01 PM, Andrii Anisov wrote:
On 08.05.19 17:31, Julien Grall wrote:
I haven't seen them with nokpti platform so far. I am curious to know
what is your configuration here.
XEN 4.12 with our patches. Thin Dom0 is a generic armv8 Linux, LK
4.14.75 with patches from Renesa
On 5/13/19 11:15 AM, Andrii Anisov wrote:
Hello Julien,
On 08.05.19 16:59, Julien Grall wrote:
Hi,
On 23/04/2019 09:10, Andrii Anisov wrote:
From: Andrii Anisov
Following discussion [1] it is introduced and implemented a runstate
registration interface which uses guest's phys ad
On 5/13/19 3:14 PM, Andrii Anisov wrote:
Hello Julien,
Hello,
On 13.05.19 14:16, Julien Grall wrote:
I am afraid I can't possible back this assumption. As I pointed out
in the previous version, I would be OK with the always map solution
on Arm32 (pending performance) because it wou
418
Which commit are you using? Do you remember which one worked? If so, can
you bisect it?
---
Julien, are you going to integrate the patch?
For that someone needs to send a patch so it can be reviewed. I was
hoping you could do that as the reporter of the problem.
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Hi,
On 5/13/19 4:29 PM, Andrii Anisov wrote:
On 13.05.19 17:34, Julien Grall wrote:
My point of my message is to understand the exact workload/setup you
are using. "dd" was not an entirely obvious choice for CPUBurn and
Google didn't provide a lot of website backing t
On 5/13/19 4:38 PM, Andrii Anisov wrote:
On 13.05.19 18:31, Julien Grall wrote:
So, are you running 4 dd (one for each core) in parallel? Are they
pinned?
Yes, sure I run 4 dd's in parallel to get all VCPUs loaded. No they are
not pinned.
From my understanding, if you want consis
Hi.
On 5/13/19 4:42 PM, Andrii Anisov wrote:
On 13.05.19 18:40, Julien Grall wrote:
From my understanding, if you want consistency, then setting the
affinity will definitely help. Otherwise, you may have the scheduler
to kick up and also balancing.
Sorry, do you mean setting affinity for dd
endent components (say boot loader and
OS) may need to be permitted to chose models independently of
one another.
Good point. On a similar topic, how does Kexec works on Xen? Do we reset the
domain as well?
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On 13/05/2019 13:30, Andrii Anisov wrote:
On 08.05.19 18:40, Julien Grall wrote:
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 6dc633e..8e24e63 100644
{
- void __user *guest_handle = NULL;
+ if ( !guest_handle_is_null(runstate_guest(v)) )
+ {
+ void
On 14/05/2019 11:08, Andrii Anisov wrote:
Hello Julien,
On 14.05.19 12:58, Julien Grall wrote:
I guess we should agree what to implement first.
I think there are an agreement that the two methods should not be used together.
For a domain or for a particular VCPU?
How should we response
hat I asked. What I asked is whether Xen is involved when a guest
kernel is kexecing to another kernel.
I don't know enough Kexec to be able to answer that question myself.
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would
need to invalidate the instruction cache.
So rather than keeping around the function flush_xen_text_tlb_local()
replace it with call to flush_xen_tlb_local() and explicitely flush
the cache when necessary.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v3
ff-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v3:
- Update commit message
- Fix typoes
Changes in v2:
- Add Andrii's reviewed-by
---
xen/arch/arm/mm.c| 18 +-
xen/include/asm-arm/arm32/page.h | 15 +-
At the moment, create_xen_entries will only flush the TLBs if the full
range has successfully been updated. This may lead to leave unwanted
entries in the TLBs if we fail to update some entries.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
Reviewed-by: Stefano Stabellini
part over the next few weeks.
In this first part, I focus on reworking how we flush the TLBs in Xen.
The main addition for this version is to prevent Xen booting on AIVIVT
instruction caches (see patch #1). For all the other changes, see each patch.
Cheers,
Julien Grall (8):
xen/arm: Don't b
TLB helpers in the headers tlbflush.h are currently quite confusing to
use the name may lead to think they are dealing with hypervisors TLBs
while they actually deal with guest TLBs.
Rename them to make it clearer that we are dealing with guest TLBs.
Signed-off-by: Julien Grall
Reviewed-by
can only boot on a small
number of processors (see arch/arm/arm32/proc-v7.S). All of them are
not using AIVIVT cache.
Signed-off-by: Julien Grall
---
Changes in v3:
- Patch added
---
xen/arch/arm/setup.c| 5 +
xen/include/asm-arm/processor.h | 5 +
2 files changed
The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
non-boot CPU. So introduce a function to set the bit and clear TLBs.
This new function will help us to document and update the logic in a
single place.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
Reviewed-by: Stefano
are a lack of documentation in most of the TLBs helper.
Rather than trying to update the helpers one by one, this patch
introduce a per-arch macro to generate the TLB helpers. This will be
easier to update the TLBs helper in the future and the documentation.
Signed-off-by: Julien Grall
Reviewed
At the moment, TLB helpers are scattered in 2 headers: page.h (for
Xen TLB helpers) and tlbflush.h (for guest TLB helpers).
This patch is gathering all of them in tlbflush. This will help to
uniformize and update the logic of the helpers in follow-up patches.
Signed-off-by: Julien Grall
None of the parameters of secondary_start are actually used. So turn
secondary_start to a function with no parameters.
Also modify the assembly code to avoid setting-up the registers before
calling secondary_start.
Signed-off-by: Julien Grall
- Re-order the patch with "xen/arm: R
e
used by anyone in Xen and also avoid to include bitops.h in assembly
code.
Signed-off-by: Julien Grall
---
Changes in v2:
- Replace "xen/const: Introduce _BITUL and _BITULL"
---
xen/arch/arm/arm32/insn.c | 2 +-
xen/arch/arm/arm64/insn.c | 18 +---
would
need to invalidate the instruction cache.
So rather than keeping around the function flush_xen_text_tlb_local()
replace it with call to flush_xen_tlb_local() and explicitely flush
the cache when necessary.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v3
easy to get out-of-sync with the definitions.
Signed-off-by: Julien Grall
---
Changes in v2:
- Use BIT(..., UL) instead of _BITUL
---
xen/arch/arm/arm32/head.S | 12 +
xen/arch/arm/arm64/head.S | 10 +---
xen/include/asm-arm/processor.h | 54
The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
non-boot CPU. So introduce a function to set the bit and clear TLBs.
This new function will help us to document and update the logic in a
single place.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
Reviewed-by: Stefano
ff-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v3:
- Update commit message
- Fix typoes
Changes in v2:
- Add Andrii's reviewed-by
---
xen/arch/arm/mm.c| 18 +-
xen/include/asm-arm/arm32/page.h | 15 +-
to be used).
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2:
- Fix build on arm32
- Add Andrii's reviewed-by
---
xen/arch/arm/arm32/head.S | 5 +++--
xen/arch/arm/arm64/head.S | 4 ++--
xen/arch/arm/guest_walk.c | 2 +-
xen
At the moment, create_xen_entries will only flush the TLBs if the full
range has successfully been updated. This may lead to leave unwanted
entries in the TLBs if we fail to update some entries.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
Reviewed-by: Stefano Stabellini
Use the pattern BIT(..., UL) to make the code more readable. Note that
unsigned long is used instead of unsigned because SCTLR is technically
32-bit on Arm32 and 64-bit on Arm64.
Signed-off-by: Julien Grall
---
Changes in v2:
- Rework the patch to use BIT(..., UL) instead of _BITUL
TLB helpers in the headers tlbflush.h are currently quite confusing to
use the name may lead to think they are dealing with hypervisors TLBs
while they actually deal with guest TLBs.
Rename them to make it clearer that we are dealing with guest TLBs.
Signed-off-by: Julien Grall
Reviewed-by
system.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2:
- Add Andrii's reviewed-by
---
xen/arch/arm/arm64/head.S | 6 --
1 file changed, 6 deletions(-)
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index b957eb90fb..08094
The parameter cpuid is not used by start_xen. So remove it.
Signed-off-by: Julien Grall
---
- Re-order the patch with "xen/arm: Rework secondary_start
prototype"
---
xen/arch/arm/arm32/head.S | 1 -
xen/arch/arm/arm64/head.S | 1 -
xen/arch/arm/setup.c | 3 +--
3 files
are a lack of documentation in most of the TLBs helper.
Rather than trying to update the helpers one by one, this patch
introduce a per-arch macro to generate the TLB helpers. This will be
easier to update the TLBs helper in the future and the documentation.
Signed-off-by: Julien Grall
Reviewed
At the moment, TLB helpers are scattered in 2 headers: page.h (for
Xen TLB helpers) and tlbflush.h (for guest TLB helpers).
This patch is gathering all of them in tlbflush. This will help to
uniformize and update the logic of the helpers in follow-up patches.
Signed-off-by: Julien Grall
have been initialized, so we can get backtrace if an error
occurred.
Moving the initialization of the page-tables also avoid the dance to map
the FDT again in the new set of page-tables.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2:
- Add Andrii
The page-table walker is configured to use the same shareability and
cacheability as the access performed when updating the page-tables. This
means cleaning the cache for secondary CPUs runtime page-tables is
unnecessary.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes
plied based
on staging:
git://xenbits.xen.org/people/julieng/xen-unstable.git branch mm/part2/v2
Cheers,
[1] https://lists.xenproject.org/archives/html/xen-devel/2019-05/msg01109.html
Julien Grall (19):
xen/const: Extend the existing macro BIT to take a suffix in parameter
xen/arm: Rename S
ff-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2:
- Add Andrii's reviewed-by
---
xen/arch/arm/mm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index eacc1647e0..b408de7c75 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arc
instructions before the write the
page-table entry.
Signed-off-by: Julien Grall
---
Changes in v2:
- Use 0x0 instead of 0
- Remove a duplicate mov r3, #0
---
xen/arch/arm/arm32/head.S | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/arm32
can only boot on a small
number of processors (see arch/arm/arm32/proc-v7.S). All of them are
not using AIVIVT cache.
Signed-off-by: Julien Grall
---
Changes in v3:
- Patch added
---
xen/arch/arm/setup.c| 5 +
xen/include/asm-arm/processor.h | 5 +
2 files changed
. So it is pointless to zero the domheap again.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2:
- Tweak a bit the commit message
- Add Andrii's reviewed-by
---
xen/arch/arm/mm.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/xen/arc
So far, we don't have specific core initialization at boot. So remove
the comment.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2:
- Fix typo in the commit message
- Add Andrii's reviewed-by
---
xen/arch/arm/arm64/head.S | 2 --
1 file
At the moment, set_fixmap may replace a valid entry without following
the break-before-make sequence. This may result to TLB conflict abort.
Rather than dealing with Break-Before-Make in set_fixmap, every call to
set_fixmap is paired with a call to clear_fixmap.
Signed-off-by: Julien Grall
introduced
and now used to define static page-tables.
Note that DEFINE_PAGE_TABLES() alignment differs from what is currently
used for allocating page-tables. This is fine because page-tables are
only required to be aligned to a page-size.
Signed-off-by: Julien Grall
---
Changes in v2
At the moment, the earlyprintk messages are interleaved with the
instructions. This makes more difficult to read the objdump output.
Introduce a new macro to add a string in .rodata.str and use it for all
the earlyprintk messages.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
I
system.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2:
- Add Andrii's reviewed-by
---
xen/arch/arm/arm32/head.S | 8
1 file changed, 8 deletions(-)
diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index 9f40face98..d42a1
pretty hard to reach as page-tables are allocated
once and never released. Yet it is possible, so we need to protect with
a spinlock to avoid corrupting the page-tables.
Signed-off-by: Julien Grall
---
Changes in v2:
- Rework the commit message
---
xen/arch/arm/mm.c | 6 ++
1
The co-processor registers MAIR0 and MAIR1 are managed by EL1. So there
are no need to initialize them during Xen boot.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
---
Changes in v2
- Add Andrii's reviewed-by
---
xen/arch/arm/arm32/head.S | 2 --
1 file chang
Hi all,
I forgot to remove the patches for part1 before sending the part2. I will resend
the series properly.
Sorry for the noise.
Cheers,
On 14/05/2019 13:21, Julien Grall wrote:
Hi all,
This is the second part of the boot/memory rework for Xen on Arm. This
part contains mostly clean-up
The parameter cpuid is not used by start_xen. So remove it.
Signed-off-by: Julien Grall
---
- Re-order the patch with "xen/arm: Rework secondary_start
prototype"
---
xen/arch/arm/arm32/head.S | 1 -
xen/arch/arm/arm64/head.S | 1 -
xen/arch/arm/setup.c | 3 +--
3 files
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