On Wed, Mar 20, 2024 at 07:58:05PM +0100, Oleksii wrote:
> On Mon, 2024-03-18 at 17:58 +0100, Jan Beulich wrote:
> > On 15.03.2024 19:05, Oleksii Kurochko wrote:
> > > Currently, RISC-V requires two extensions: _zbb and _zihintpause.
> >
> > Do we really require Zbb already?
> After an introductio
On Thu, Mar 21, 2024 at 09:31:59AM +0100, Jan Beulich wrote:
> On 20.03.2024 20:44, Conor Dooley wrote:
> > On Wed, Mar 20, 2024 at 07:58:05PM +0100, Oleksii wrote:
> >> On Mon, 2024-03-18 at 17:58 +0100, Jan Beulich wrote:
> >>> On 15.03.2024 19:05, Oleksii Kurochko
On Thu, Feb 06, 2025 at 02:05:31PM +0100, Oleksii Kurochko wrote:
> On 2/5/25 8:07 PM, Conor Dooley wrote:
> > On Thu, Jan 23, 2025 at 03:46:36PM +0100, Oleksii Kurochko wrote:
> > > Supported ISA extensions are specified in the device tree within the CPU
> > > node, u
Yo,
On Thu, Jan 23, 2025 at 03:46:36PM +0100, Oleksii Kurochko wrote:
> Supported ISA extensions are specified in the device tree within the CPU
> node, using two properties: `riscv,isa-extensions` and `riscv,isa`.
>
> Currently, Xen does not support the `riscv,isa-extensions` property, as
> all
