From: Brendan Kerrigan
The Intel IOMMU for at least 8th and 9th generation Core processors has a bug
where the Fault Processing Disable bit is not respected for the Intel Graphics
Device (IGD). The resulting behavior was reported previously[1]. The underlying
cause is described by Intel as
From: Brendan Kerrigan
The Intel graphics device records DMAR faults regardless
of the Fault Process Disable bit being set. When this fault
occurs, enable the Interrupt Mask (IM) bit in the Fault
Event Control (FECTL) register to prevent the continued
recording of the fault.
Signed-off-by
blem.
-Brendan
On Sun, Apr 19, 2020 at 11:28 PM Tian, Kevin wrote:
> > From: Brendan Kerrigan
> > Sent: Friday, April 17, 2020 9:36 PM
> >
> > From: Brendan Kerrigan
> >
> > The Intel graphics device records DMAR faults regardless
> > of the Fault Proc
# Design Session Notes - "How best to upstream Bareflank's implementation
of the Xen VMM into the Xen Project"
## Design Session Description
Assured Information Security, Inc. has been working on a new implementation
of the Xen VMM (i.e., just the root component of the Xen hypervisor) using
Barefla
