Hi,
On 09/02/18 19:27, Julien Grall wrote:
> Hi,
>
> On 02/09/2018 02:38 PM, Andre Przywara wrote:
>> The VGIC model used for a domain (GICv2 or GICv3) determines the maximum
>> number of VCPUs for that guest, as GICv2 can only handle 8 processors.
>> In the moment w
Hi,
On 26/02/18 16:30, Julien Grall wrote:
>
>
> On 02/26/2018 04:25 PM, Andre Przywara wrote:
>> Hi,
>>
>> On 26/02/18 15:55, Julien Grall wrote:
>>> Hi,
>>>
>>> On 02/26/2018 03:29 PM, Andre Przywara wrote:
>>>> On 13/02/1
Hi,
On 19/02/18 15:43, Julien Grall wrote:
>
>
> On 19/02/18 15:32, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 16/02/18 17:16, Julien Grall wrote:
>>> On 09/02/18 14:39, Andre Przywara wrote:
>>>> +
>>>> + /* Loop
On Thu, 22 Nov 2018 18:51:13 +0200
Andrii Anisov wrote:
Hi,
> On 20.11.18 20:47, Julien Grall wrote:
> >
> >
> > On 20/11/2018 18:10, Andrii Anisov wrote:
> >> Hello Julien,
> >>
> >>
> >> On 19.11.18 18:42, Julien Grall wrote:
> >>> There are no issue about processing IRQs before the sync
On Fri, 23 Nov 2018 12:09:41 +0200
Andrii Anisov wrote:
Hi,
> On 22.11.18 19:22, Julien Grall wrote:
> > My biggest worry is you are doing optimization on a vGIC that is
> > not fully compliant with how a GIC should behave (e.g edge vs
> > level) and with very fragile locking.
> Yep, old VGIC
Architecturally there is only one GICv3 redistributor region.
Drop the symbol which suggested that was a delibarate choice for Xen
guests, instead hard code the "1" in the appropriate places, along with
a comment to explain the reasons.
Signed-off-by: Andre Przywara
---
xen/arch/arm
r, by simplifying
it for the host GICv3 driver, and removing it at all from the VGIC.
Cheers,
Andre
Andre Przywara (7):
tools: ARM: vGICv3: avoid inserting optional DT properties
ARM: vGICv3: drop GUEST_GICV3_RDIST_REGIONS symbol
ARM: GICv3: emit optional DT property only when necessary
ARM:
value.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v3.c | 3 +--
xen/arch/arm/vgic-v3.c| 14 --
xen/include/asm-arm/domain.h | 1 -
xen/include/asm-arm/vgic.h| 1 -
xen/include/public/arch-arm.h | 2 --
5 files changed, 1 insertion(+), 20 deletions(-)
Instead of hard coding the architected redistributor stride into the
code, lets use a clear #define to the two values for GICv3 and GICv4 and
clarify the algorithm to determine the needed stride value.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v3.c | 18
dware domain.
This avoids the hardware GIC code to reference vGIC data structures,
making this variable VGIC internal.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v3.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arc
The ARM GICv3 DT property "#redistributor-regions" is optional and only
useful if it has any other values than the architected "1".
Keep our generated DT node clean by emitting this property only if we
actually need more than one region.
Signed-off-by: Andre Przywara
---
x
architected one. This will never be the case for the
constructed DomU memory map.
So we drop those properties altogether and provide a clean and architected
GICv3 DT node for DomUs.
Signed-off-by: Andre Przywara
---
tools/libxl/libxl_arm.c | 8
1 file changed, 8 deletions(-)
diff --git a
27;s GICv3
emulation.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v3.c | 5 -
xen/arch/arm/vgic-v3.c | 14 ++
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 2893c66492..1684d9cf1b 100644
--- a/xen/arch/arm/gic
Hi,
On 24/01/18 16:08, Julien Grall wrote:
> (+ Tools maintainers)
>
> Hi Andre,
>
> On 24/01/18 14:35, Andre Przywara wrote:
>> When creating a GICv3 devicetree node, we currently insert the
>> redistributor-stride and #redistributor-regions properties, with fixed
&
Hi,
On 24/01/18 16:13, Julien Grall wrote:
> Hi Andre,
>
> On 24/01/18 14:35, Andre Przywara wrote:
>> Architecturally there is only one GICv3 redistributor region.
>> Drop the symbol which suggested that was a delibarate choice for Xen
>> guests, instead hard code
Hi,
On 24/01/18 16:32, Julien Grall wrote:
> Hi Andre,
>
> On 24/01/18 14:35, Andre Przywara wrote:
>> The ARM GICv3 DT property "#redistributor-regions" is optional and only
>> useful if it has any other values than the architected "1".
>> Ke
Hi,
sorry for the delay on this, I just found this in preparation for a repost.
On 08/12/17 21:40, Stefano Stabellini wrote:
> On Thu, 7 Dec 2017, Andre Przywara wrote:
>> In gic_restore_pending_irqs() we push our pending virtual IRQs into the
>> list registers. This function is c
e the author) and will be addressed later.
Andre Przywara (8):
ARM: VGIC: drop unneeded gic_restore_pending_irqs()
ARM: VGIC: split gic.c to observe hardware/virtual GIC separation
ARM: VGIC: split up gic_dump_info() to cover virtual part separately
ARM: VGIC: rework events_need_delivery()
The functions to actually populate a list register were accessing
the VGIC internal pending_irq struct, although they should be abstracting
from that.
Break the needed information down to remove the reference to pending_irq
from gic-v[23].c.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano
At the moment we happily access the VGIC internal struct pending_irq
(which describes a virtual IRQ) in irq.c.
Factor out the actually needed functionality to learn the associated
hardware IRQ and move that into gic-vgic.c to improve abstraction.
Signed-off-by: Andre Przywara
Acked-by: Stefano
separate file,
so that gic.c does what it says on the tin.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano Stabellini
---
xen/arch/arm/Makefile | 1 +
xen/arch/arm/gic-vgic.c | 410
xen/arch/arm/gic.c | 363
Currently gic_dump_info() not only dumps the hardware state of the GIC,
but also the VGIC internal virtual IRQ lists.
Split the latter off and move it into gic-vgic.c to observe the abstraction.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano Stabellini
---
xen/arch/arm/domain.c | 1
said accesses to VGIC data structures and improves abstraction.
Signed-off-by: Andre Przywara
Acked-by: Stefano Stabellini
---
xen/arch/arm/gic-vgic.c| 31 +++
xen/arch/arm/gic.c | 42 ++
xen/include/asm-arm/vgic.h | 2
needed, since we will always call gic_inject() anyway.
So remove that call (and the forward declaration) to streamline this
interface and make separating the GIC from the VGIC world later.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic.c | 4
1 file changed, 4 deletions(-)
diff --git a
In event.h we very deeply dive into the VGIC to learn if an event for
a guest is pending.
Rework that function to abstract the VGIC specific part out. Also
reorder the queries there, as we only actually need to check for the
event channel if there are no other pending IRQs.
Signed-off-by: Andre
On ARM the maximum number of IRQs is a constant, but we share it being
a variable to match x86. Since we are not supposed to alter it, let's
mark it as "const" to avoid accidental change.
Suggested-by: Julien Grall
Signed-off-by: Andre Przywara
---
xen/arch/arm/irq.c| 2
Hi,
(CC:ing Edgar)
On 25/01/18 15:03, Amit Singh Tomar wrote:
> This seems to be copy/paste error.This patch simply
> replace string xgene_storm with xilink_zymp for xilink
> platform.
>
> Signed-off-by: Amit Singh Tomar
> ---
> xen/arch/arm/platforms/xilinx-zynqmp.c | 2 +-
> 1 file changed,
On Wed, 24 Jul 2019 14:34:55 +
Stewart Hildebrand wrote:
Hi,
I am afraid this is not enough. In your repo you hack the DT to contain
the reg-shift and io-width properties, but those are not part of the
"brcm,bcm2835-aux-uart" binding. Using 32-bit accesses is an integral
property of this UAR
On Mon, 24 Jan 2022 17:58:55 +
Julien Grall wrote:
Hi Julien,
> Hi Andre,
>
> On 24/01/2022 14:36, Andre Przywara wrote:
> > On Mon, 24 Jan 2022 12:07:42 +
> >> Also, if an instruction is being modified by the guest (after it has
> >> been loaded
On Tue, 15 Jun 2021 07:12:08 +0100
Wei Chen wrote:
Hi Wei,
> I have some thoughts of using kvmtool Virtio implementation
> for Xen. I copied my markdown file to this email. If you have
> time, could you please help me review it?
>
> Any feedback is welcome!
>
> # Some thoughts on using kvmtool
On Wed, 30 Nov 2022 08:09:53 +0100
Jan Beulich wrote:
Hi Ayan,
> On 29.11.2022 19:18, Ayan Kumar Halder wrote:
> > On 29/11/2022 15:52, Julien Grall wrote:
> >> On 29/11/2022 16:23, Ayan Kumar Halder wrote:
> >>> On 29/11/2022 14:52, Julien Grall wrote:
> On 29/11/2022 14:57, Ayan Kum
On Wed, 30 Nov 2022 15:39:56 +
Ayan Kumar Halder wrote:
Hi Ayan,
> On 30/11/2022 13:13, Andre Przywara wrote:
> > On Wed, 30 Nov 2022 08:09:53 +0100
> > Jan Beulich wrote:
> >
> > Hi Ayan,
> Hi Andre,
> >
> >> On 29.11.2022 19:18, Ayan Ku
On Fri, 19 Nov 2021 16:52:02 +
Ayan Kumar Halder wrote:
Hi,
> At present, post indexing instructions are not emulated by Xen.
> When Xen gets the exception, EL2_ESR.ISV bit not set. Thus as a
> result, data abort is triggered.
>
> Added the logic to decode ldr/str post indexing instructions
On Fri, 26 Nov 2021 15:28:06 +
Ayan Kumar Halder wrote:
Hi Ayan,
> Many thanks for your inputs.
> Apologies if I sound dumb, but I need a few clarifications.
>
> On 26/11/2021 13:14, Andre Przywara wrote:
> > On Fri, 19 Nov 2021 16:52:02 +
> > Ayan Kumar Ha
On Mon, 29 Nov 2021 19:16:38 +
Ayan Kumar Halder wrote:
Hi,
> At the moment, Xen is only handling data abort with valid syndrome (i.e.
> ISV=0). Unfortunately, this doesn't cover all the instructions a domain
> could use to access MMIO regions.
>
> For instance, Xilinx baremetal OS will use
On Wed, 1 Dec 2021 08:41:13 +
Bertrand Marquis wrote:
Hi,
> > On 30 Nov 2021, at 19:13, Ayan Kumar Halder
> > wrote:
> >
> > Hi Andre,
> >
> > Thanks for your comments. They are useful.
> >
> > On 30/11/2021 09:49, Andre Przywara wrote:
&
On Tue, 30 Nov 2021 19:13:41 +
Ayan Kumar Halder wrote:
Hi Ayan,
> Thanks for your comments. They are useful.
>
> On 30/11/2021 09:49, Andre Przywara wrote:
> > On Mon, 29 Nov 2021 19:16:38 +
> > Ayan Kumar Halder wrote:
> >
> > Hi,
> >
&
nks for your comments. They are useful.
> >>
> >> On 30/11/2021 09:49, Andre Przywara wrote:
> >>> On Mon, 29 Nov 2021 19:16:38 +
> >>> Ayan Kumar Halder wrote:
> >>> Hi,
> >>>> At the moment, Xen is only handling data abor
On Wed, 5 Jan 2022 16:55:11 +
Ayan Kumar Halder wrote:
Hi,
> Thank you so much for your feedback.
>
> I need a couple of clarifications before I can start with the v3 patch.
>
> On 08/12/2021 12:00, Andre Przywara wrote:
> > On Mon, 6 Dec 2021 19:31:06 +
&g
On Mon, 10 Jan 2022 14:33:11 +
Ayan Kumar Halder wrote:
Hi Ayan,
> Many thanks for your inputs. It is making better sense now. Much
> appreciated.
>
> A few questions/clarifications :-
>
> On 06/01/2022 15:33, Andre Przywara wrote:
> > On Wed, 5 Jan 2022 16:55
On Thu, 20 Jan 2022 21:55:27 +
Ayan Kumar Halder wrote:
Hi,
> At the moment, Xen is only handling data abort with valid syndrome (i.e.
> ISV=0). Unfortunately, this doesn't cover all the instructions a domain
> could use to access MMIO regions.
>
> For instance, a baremetal OS can use any o
On Mon, 24 Jan 2022 12:07:42 +
Ayan Kumar Halder wrote:
Hi Ayan,
> Many thanks for your feedback. I have one clarification :-
>
> On 22/01/2022 01:30, Andre Przywara wrote:
> > On Thu, 20 Jan 2022 21:55:27 +
> > Ayan Kumar Halder wrote:
> >
> > Hi,
hing about
it, and would need to change the guest to not do so. See above what Linux
does: always access them in two chunks, so it works everywhere.
Cheers,
Andre
> However, looking at the following commit in kernel, I am a bit confused.
>
> commit 0aa1de57319c4e023187aca0d59dd593a964
dabd9ce4 ("ARM: vGICv3: handle virtual LPI pending and
> property tables")
> Signed-off-by: Ayan Kumar Halder
Indeed, the patch looks good to me. Also checked the other users of
vreg_reg64_extract(), they seem to be all correct, by first building
the value, then running the extract
On Tue, 25 Oct 2022 13:25:52 +0100
Ayan Kumar Halder wrote:
Hi,
> Hi Andre/All,
>
> This came up while porting Xen on R52.
>
> Refer "ARM DDI 0568A.cID110520", B1.3.1
>
> "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE
> must not implement LPI support. "
>
> Does this m
On Wed, 26 Oct 2022 19:30:04 +0100
Ayan Kumar Halder wrote:
Hi,
> If a guest is running in 32 bit mode and it tries to access
> "GICR_PENDBASER + 4" mmio reg, it will be trapped to Xen. vreg_reg64_extract()
> will return the value stored "v->arch.vgic.rdist_pendbase + 4".
> This will be stored i
On Thu, 27 Oct 2022 14:38:52 +0100
Ayan Kumar Halder wrote:
Hi Ayan,
> On 25/10/2022 14:55, Andre Przywara wrote:
> > On Tue, 25 Oct 2022 13:25:52 +0100
> > Ayan Kumar Halder wrote:
> >
> > Hi,
>
> Hi Andre,
>
> Many thanks for the explanation.
>
On Thu, 27 Oct 2022 16:40:01 +0100
Ayan Kumar Halder wrote:
Hi Ayan,
> On 27/10/2022 10:44, Andre Przywara wrote:
> > On Wed, 26 Oct 2022 19:30:04 +0100
> > Ayan Kumar Halder wrote:
> >
> > Hi,
>
> Hi Andre,
>
> I need a clarification.
>
> >
t; used to restore the saved interrupt state.
>
> Fixes: fe7fa1332dabd9ce4 ("ARM: vGICv3: handle virtual LPI pending and
> property tables")
> Signed-off-by: Ayan Kumar Halder
Thanks for fixing this!
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> xen/arch/arm/vgic-v3.
4 ("ARM: vGICv3: handle virtual LPI pending and
> property tables")
> Signed-off-by: Ayan Kumar Halder
> Release-acked-by: Henry Wang
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
>
> Changes from:-
>
> v1 - 1. Extracted this fix from "[RFC PA
On Fri, 28 Oct 2022 12:44:08 +0100
Ayan Kumar Halder wrote:
> On 27/10/2022 15:36, Andre Przywara wrote:
> > On Thu, 27 Oct 2022 14:38:52 +0100
> > Ayan Kumar Halder wrote:
> >
> > Hi Ayan,
> Hi Andre / Julien,
> >
> >> On 25/10/2022 14:55, Andr
On Thu, 10 Nov 2022 12:32:49 -0800 (PST)
Stefano Stabellini wrote:
Hi,
> On Wed, 9 Nov 2022, Michal Orzel wrote:
> > Hi Jiamei,
> >
> > On 09/11/2022 09:25, Jiamei Xie wrote:
> > >
> > >
> > > Hi Michal，
> > >
> > > Below log can be got when stating the linux guest. It says 9c09 is sbsa.
401 - 452 of 452 matches
Mail list logo
