separate file,
so that gic.c does what it says on the tin.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen/arch/arm/Makefile | 1 +
xen/arch/arm/gic-vgic.c | 396 ++
xen/arch/arm/gic.c| 363
pend on a clean separation, so this
series tries to clean this up.
After this series there are no more references to VGIC structures from
GIC files, at least for non-ITS code. The ITS is a beast own its own
(blame the author) and will be addressed later.
*** BLURB HERE ***
Andre Przywara (8):
ARM: V
needed, since we will always call gic_inject() anyway.
So remove that call (and the forward declaration) to streamline this
interface and make separating the GIC from the VGIC world later.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
Reviewed-by: Stefano Stabellini
---
xen/arch/arm
ny adverse effect, but is a change in locking anyway.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-vgic.c| 41 +
xen/arch/arm/gic.c | 44 ++--
xen/include/asm-arm/vgic.h | 2 ++
3 files changed, 53
On ARM the maximum number of IRQs is a constant, but we share it being
a variable to match x86. Since we are not supposed to alter it, let's
mark it as "const" to avoid accidental change.
Suggested-by: Julien Grall
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen
The functions to actually populate a list register were accessing
the VGIC internal pending_irq struct, although they should be abstracting
from that.
Break the needed information down to remove the reference to pending_irq
from gic-v[23].c.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano
iate if somehow could have a look at those patches, patch 20
and following are surely the most interesting ones to have a look at.
Cheers,
Andre
Andre Przywara (49):
tools: ARM: vGICv3: avoid inserting optional DT properties
ARM: vGICv3: drop GUEST_GICV3_RDIST_REGIONS symbol
ARM: GICv3: use
value.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v3.c | 3 +--
xen/arch/arm/vgic-v3.c| 14 --
xen/include/asm-arm/domain.h | 1 -
xen/include/asm-arm/vgic.h| 1 -
xen/include/public/arch-arm.h | 2 --
5 files changed, 1 insertion(+), 20 deletions(-)
Architecturally there is only one GICv3 redistributor region.
Drop the symbol which suggested that was a delibarate choice for Xen
guests, instead hard code the "1" in the appropriate places, along with
a comment to explain the reasons.
Signed-off-by: Andre Przywara
---
xen/arch/arm
So far the number of list registers (LRs) a GIC implements is only
needed in the hardware facing side of the VGIC code (gic-vgic.c).
The new VGIC will need this information in more and multiple places, so
export a function that returns the number.
Signed-off-by: Andre Przywara
---
xen/arch/arm
t least prepares the callers
to do the right thing later automatically.
Signed-off-by: Andre Przywara
---
xen/arch/arm/domain.c | 4 ++--
xen/arch/arm/gic-v3-lpi.c | 2 +-
xen/arch/arm/irq.c | 2 +-
xen/arch/arm/time.c| 2 +-
xen/arch/ar
definition of these
embedded structures into vgic.h, and just use the opaque type in the arch
specific structures.
This allows easy switching between different implementations later.
Signed-off-by: Andre Przywara
---
xen/include/asm-arm/domain.h | 85
27;s GICv3
emulation.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v3.c | 5 -
xen/arch/arm/vgic-v3.c | 14 ++
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 7837d93dc1..02c85e4c0c 100644
--- a/xen/arch/arm/gic
pending state of a
particular interrupt. Due to hardware limitations this only works for
private interrupts of the current CPU, so there is not CPU field in the
prototype.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v2.c | 6 ++
xen/arch/arm/gic-v3.c | 13 +
xen/arch
dware domain.
This avoids the hardware GIC code to reference vGIC data structures,
making this variable VGIC internal.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v3.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic
The new VGIC will shortly use more bits of the GICC_CTLR register, so
add the respective definitions from the manual.
Also add a missing definition for GICV_PMR_PRIORITY_MASK.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v2.c | 2 +-
xen/include/asm-arm/gic.h | 18
evtchn_upcall_pending variable to make the interrupt
line match its status, and call this function upon every hypervisor
entry.
Signed-off-by: Andre Przywara
---
xen/arch/arm/domain.c | 7 +++
xen/arch/arm/traps.c| 1 +
xen/include/asm-arm/event.h | 1 +
3 files changed, 9 insertions
vGIC (and the LR).
The VGIC in Xen so far only implemented edge triggered vIRQs, really, so
we need to add new functionality to re-sample the interrupt state.
Signed-off-by: Andre Przywara
---
xen/arch/arm/time.c | 34 ++
xen/arch/arm/traps.c| 1 +
xen
.
This is based on Linux commit 2b0cda878965, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 48 +++-
xen/arch/arm/vgic/vgic.c | 15 +
xen/arch/arm/vgic/vgic.h | 4
3 files changed, 66
The emulated ARM SBSA UART is using level triggered IRQ semantics,
however the current VGIC can only handle edge triggered IRQs, really.
Disable the existing workaround for this problem in case we have the
new VGIC in place, which can properly handle level triggered IRQs.
Signed-off-by: Andre
2c234d6f1826, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 52 +++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c
index c0b88b347e
interrupts and SPIs, but handles the ref-counting for LPIs.
This is based on Linux commit 64a959d66e47, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 107 +++
xen/arch/arm/vgic/vgic.h | 32 ++
2
VGIC implementation details to generic Xen code.
Add a new arch specific field in our domain structure to hold this vcpu limit,
and initialize it when we set the ops. This allows us to plug in the new
VGIC later without also needing to carry some ops structure.
Signed-off-by: Andre Przywara
The prototype for gic_remove_from_lr_pending() is the last function in
gic.h which references a VGIC data structure.
Move it over to vgic.h, so that we can remove the inclusion of vgic.h
from gic.h. We add it to asm/domain.h instead, where it is actually
needed.
Signed-off-by: Andre Przywara
ed in the
following patches.
This is based on Linux commit 0919e84c0fc1, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 246 +++
xen/arch/arm/vgic/vgic.h | 2 +
2 files changed, 248 insertions(+)
diff --git
setup the host GIC addresses.
This is based on Linux commit 140b086dd197, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-v2.c | 261
xen/arch/arm/vgic/vgic.c| 20
xen/arch/arm/vgic/vgic.h| 8 ++
3
to avoid touching all the users.
This is based on Linux commit b18b57787f5e, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
xen/include/asm-arm/arm_vgic.h | 269 +
xen/include/asm-arm/domain.h | 4 +
xen/include/asm-arm/vgic.h | 6
IRQ.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v2.c | 9 +
xen/arch/arm/gic-v3.c | 16
xen/arch/arm/gic.c| 5 +
xen/include/asm-arm/gic.h | 5 +
4 files changed, 35 insertions(+)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic
: add proper value for GICv2 on GICv3 emulation!
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v2.c | 3 ++-
xen/arch/arm/gic-v3.c | 3 ++-
xen/arch/arm/vgic-v2.c | 3 ++-
xen/include/asm-arm/vgic.h | 3 ++-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/xen/arch
Marc Zyngier.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio.c | 192 ++
xen/arch/arm/vgic/vgic-mmio.h | 145 +++
xen/arch/arm/vgic/vgic.h | 4 +
3 files changed, 341 insertions(+)
create mode 100644 xen/arch/arm
Instead of hard coding the architected redistributor stride into the
code, lets use a clear #define to the two values for GICv3 and GICv4 and
clarify the algorithm to determine the needed stride value.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v3.c | 18
This patch allocates and initializes the data structures used to model
the vgic distributor and virtual cpu interfaces. At that stage the
number of IRQs and number of virtual CPUs is frozen.
This is based on Linux commit ad275b8bb1e6, written by Eric Auger.
Signed-off-by: Andre Przywara
extra logic to properly track
the active state.
For clearing the active state, we would basically have to halt the guest
to make sure this is properly propagated into the respective VCPUs.
This is not yet implemented in Xen.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 4
As the enable register handlers are shared between the v2 and v3
emulation, their implementation goes into vgic-mmio.c, to be easily
referenced from the v3 emulation as well later.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +-
xen/arch/arm/vgic/vgic-mmio.c
As this register is v2 specific, its implementation lives entirely
in vgic-mmio-v2.c.
This register allows setting the source mask of an IPI.
This is based on Linux commit ed40213ef9b0, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 77
can't
easily reuse the existing implementation.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 44
1 file changed, 44 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index b62cda7d2f..3b475ed1a4 1
patch.
This is based on Linux commit 81eeb95ddbab, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 224 +++
xen/arch/arm/vgic/vgic.h | 10 +++
2 files changed, 234 insertions(+)
diff --git a/xen/arch/arm/vgic/vgi
Currently vgic.h both contains prototypes used by Xen arch code outside
of the actual VGIC (for instance vgic_vcpu_inject_irq()), and prototypes
for functions used by the VGIC internally.
Group them to later allow an easy split with one #ifdef.
Signed-off-by: Andre Przywara
---
xen/include/asm
The Xen core/arch code relies on two abstracted functions to inject an
event channel IRQ and to query its pending state.
Implement those to query the state of the new VGIC implementation.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 20
1 file changed, 20
there is no real technical
reason this struct has to fit in one page, so lifting the limit to two
pages seems like the most pragmatic solution.
Signed-off-by: Andre Przywara
---
xen/arch/arm/domain.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/domain.c
Tell Xen whether a particular VCPU has an IRQ that needs handling
in the guest. This is used to decide whether a VCPU is runnable.
This is based on Linux commit 90eee56c5f90, written by Eric Auger.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 32
Triggering an IPI via this register is v2 specific, so the
implementation lives entirely in vgic-mmio-v2.c.
This is based on Linux commit 55cc01fb9004, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 47 +++-
1
on Linux commit fb848db39661, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 83
xen/arch/arm/vgic/vgic-mmio.c| 26 +
xen/arch/arm/vgic/vgic-mmio.h| 2 +
xen/arch/arm/vgic/vgic.h
Dall.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c| 59 +++
xen/common/list_sort.c | 170
xen/include/xen/list_sort.h | 11 +++
3 files changed, 240 insertions(+)
create mode 100644 xen/common/list_sort.c
create mode 1
architected one. This will never be the case for the
constructed DomU memory map.
So we drop those properties altogether and provide a clean and architected
GICv3 DT node for DomUs.
Signed-off-by: Andre Przywara
---
tools/libxl/libxl_arm.c | 8
1 file changed, 8 deletions(-)
diff --git a
-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-v2.c | 65 +
xen/arch/arm/vgic/vgic.h| 1 +
2 files changed, 66 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c
index 10fc467ffa..b5026bb050 100644
--- a/xen/arch/arm
n the moment this is restricted to a vGIC-v2. To make the build system
happy, we provide a temporary dummy implementation of
vgic_v3_setup_hw() to allow building for now.
Signed-off-by: Andre Przywara
---
xen/arch/arm/Kconfig | 6 +-
xen/arch/arm/Makefile| 10 +-
xen/arch/
oment.
This is based on Linux commit dd238ec2b87b, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 4 ++--
xen/arch/arm/vgic/vgic-mmio.c| 47
xen/arch/arm/vgic/vgic-mmio.h| 7 ++
xen/arch/arm/vgic/v
The Xen arch code traps system registers writes from the guest and will
relay anything GIC related to the VGIC.
Since this affects only GICv3 (which we don't yet emulate), provide a
stub implementation of vgic_emulate() for now.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.
When we dump guest state on the Xen console, we also print the state of
IRQs that are on a VCPU.
Add the code to dump the state of an IRQ handled by the new VGIC.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/xen
This patch implements the function which is called by Xen when it wants
to register the virtual GIC.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-init.c | 62 +++
xen/arch/arm/vgic/vgic.h | 3 +++
2 files changed, 65 insertions
Enable the VGIC operation by properly initialising the registers
in the hypervisor GIC interface.
This is based on Linux commit f7b6985cc3d0, written by Eric Auger.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-v2.c | 13 +
xen/arch/arm/vgic/vgic.h| 1 +
2 files
on to make the linker happy.
Similarily vgic_clear_pending_irqs() is required by the ARM code,
although it is suspected that it is actually not necessary. Go with a
stub for now.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 13 +
1 file changed, 13 insertions(+)
diff
physical world.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 63
1 file changed, 63 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index dc5e011fa3..8d5260a7db 100644
--- a/xen/arch/arm/vgic/vgic.c
+++ b
The config register handlers are shared between the v2 and v3 emulation,
so their implementation goes into vgic-mmio.c, to be easily referenced
from the v3 emulation as well later.
This is based on Linux commit 79717e4ac09c, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
xen/arch
combine it with the
device's level to get the actual pending state.
This is based on Linux commit 96b298000db4, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +--
xen/arch/arm/vgic/vgic-mmio.c
Hi,
On 09/02/18 14:38, Andre Przywara wrote:
> tl;dr: More preparatory patches from patch 07, actual new VGIC starting
> at patch 20.
> =
>
> During development of the Dom0 ITS MSI support last year we realised
> that the existing GIC interrupt controller
Hi,
On 12/02/18 11:48, Julien Grall wrote:
>
>
> On 09/02/18 15:06, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 09/02/18 14:38, Andre Przywara wrote:
>>> tl;dr: More preparatory patches from patch 07, actual new VGIC starting
>>&g
Hi,
On 12/02/18 11:15, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:38, Andre Przywara wrote:
>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
>> index 5f47aa84a9..2fc6e19625 100644
>> --- a/xen/arch/arm/vgic.c
>> +++ b/xen/arch/arm/v
Hi,
On 12/02/18 12:19, Julien Grall wrote:
>
>
> On 12/02/18 11:59, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 12/02/18 11:15, Julien Grall wrote:
>>> Hi Andre,
>>>
>>> On 09/02/18 14:38, Andre Przywara wrote:
>>>&
Hi,
On 12/02/18 13:55, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> When playing around with hardware mapped, level triggered virtual IRQs,
>> there is the need to explicitly set the active state of an interrupt at
>> some point in
Hi,
On 12/02/18 15:19, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> The ARM Generic Timer uses a level-sensitive interrupt semantic. We
>> easily catch when the line goes high, as this triggers the hardware IRQ.
>> However we ha
Hi,
On 12/02/18 17:42, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> The new VGIC implementation centers around a struct vgic_irq instance
>> per virtual IRQ.
>> Provide a function to retrieve the right instance for a given IRQ
>&g
Hi,
Christoffer, Eric, Marc,
a question about locking order between multiple IRQs below. Could you
have a brief look, please?
On 13/02/18 12:30, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> Adds the sorting function to cover the case where you
Hi,
On 13/02/18 14:31, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> +/* Requires the VCPU's ap_list_lock to be held. */
>> +static void vgic_flush_lr_state(struct vcpu *vcpu)
>> +{
>> + struct vgic_cpu *vgic_cpu
Hi,
On 13/02/18 12:02, Julien Grall wrote:
> On 12/02/18 17:53, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 12/02/18 13:55, Julien Grall wrote:
>>> Hi Andre,
>>>
>>> On 09/02/18 14:39, Andre Przywara wrote:
>>>> When pl
Hi,
On 13/02/18 12:41, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> Implement the framework for syncing IRQs between our emulation and the
>> list registers, which represent the guest's view of IRQs.
>> This is do
Hi,
On 13/02/18 16:52, Julien Grall wrote:
> Hi Andre,7
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> Add an MMIO handling framework to the VGIC emulation:
>> Each register is described by its offset, size (or number of bits per
>> IRQ, if applicable) and the read/
Hi,
On 16/02/18 15:39, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> Create vgic-mmio-v2.c to describe GICv2 emulation specific handlers
>> using the initializer macros provided by the VGIC MMIO framework.
>> Provide a function to reg
Hi,
On 16/02/18 16:57, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> As the enable register handlers are shared between the v2 and v3
>> emulation, their implementation goes into vgic-mmio.c, to be easily
>> referenced from the
Hi,
On 16/02/18 17:16, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> The pending register handlers are shared between the v2 and v3
>> emulation, so their implementation goes into vgic-mmio.c, to be easily
>> referenced from the
Hi,
On 19/02/18 13:21, Julien Grall wrote:
> Hi,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> This patch allocates and initializes the data structures used to model
>> the vgic distributor and virtual cpu interfaces. At that stage the
>> number of IRQs and numbe
Hi,
On 15/02/18 15:02, Julien Grall wrote:
> The function SMCCC_ARCH_WORKAROUND_1 will be called by the guest for
> hardening the branch predictor. So we want the handling to be as fast as
> possible.
>
> As the mitigation is applied on every guest exit, we can check for the
> call before saving
d(const struct dt_device_node
> *psci)
> return 0;
> }
>
> +static void __init psci_init_smccc(void)
> +{
> + /* PSCI is using at least SMCC 1.0 calling convention. */
SMCCC
Other than those nits it looks good.
Reviewed-by: Andre Przyw
main. Lastly, take the opportunity to switch is_thumb from int
> to bool.
>
> Signed-off-by: Julien Grall
Reviewed-by: Andre Przywara
Cheers,
Andre.
>
> ---
> Changes in v3:
> - Patch added
> ---
> xen/arch/arm/vpsci.c | 13 -
> 1 file
Hi,
On 15/02/18 15:02, Julien Grall wrote:
> Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
>
> Signed-off-by: Julien Grall
>
> ---
> Changes in v3:
> - Add the missing call to smc #0.
>
> Changes in v2:
> - Patch added
> ---
> xen/arch/arm/arm64/b
ng
> PSCI_ALREADY_ON.
>
> Signed-off-by: Julien Grall
> Reviewed-by: Volodymyr Babchuk
Given that it's safe to clobber x0/r0 on CPU_ON in PSCI 0.1, the rest
looks correct to me:
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> The reviewed-by was kept despite move th
Hi,
On 15/02/18 15:02, Julien Grall wrote:
> SMCCC 1.1 offers firmware-based CPU workarounds. In particular,
> SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254
> (CVE-2017-5715).
>
> If the hypervisor has some mitigation for this issue, report that we
> deal with it using SM
Hi,
On 21/02/18 16:41, Julien Grall wrote:
>
>
> On 21/02/18 16:34, Andre Przywara wrote:
>> Hi,
>
> Hi,
>
>> On 15/02/18 15:02, Julien Grall wrote:
>>> SMCCC 1.1 offers firmware-based CPU workarounds. In particular,
>>> SMCCC_ARCH_WORKAROUND_
Hi,
On 19/02/18 11:53, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> The target register handlers are v2 emulation specific, so their
>> implementation lives entirely in vgic-mmio-v2.c.
>> We copy the old VGIC behaviour of assigni
Hi,
On 19/02/18 12:02, Julien Grall wrote:
> Hi,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> As this register is v2 specific, its implementation lives entirely
>> in vgic-mmio-v2.c.
>> This register allows setting the source mask of an IPI.
>>
>> Thi
Hi,
On 16/02/18 17:38, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> The priority register handlers are shared between the v2 and v3
>> emulation,
>> so their implementation goes into vgic-mmio.c, to be easily referenced
>> fr
Hi,
On 16/02/18 16:57, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> As the enable register handlers are shared between the v2 and v3
>> emulation, their implementation goes into vgic-mmio.c, to be easily
>> referenced from the
Hi,
On 19/02/18 12:19, Julien Grall wrote:
> Hi,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> The VGIC supports virtual IRQs to be connected to a hardware IRQ, so
>> when a guest EOIs the virtual interrupt, it affects the state of that
>> corresponding interrupt
tabellini
Thanks, that looks good now.
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> guest_sync only handle 64-bit guest, so I have only implemented the
> 64-bit side for now. We can discuss whether it is useful to
> implement it for 32-bit guests.
>
> We
Hi,
On 23/02/18 18:57, Julien Grall wrote:
> Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
>
> Signed-off-by: Julien Grall
Thanks, that looks good now:
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> Changes in v5:
> - Fold the fix
Hi,
On 24/02/18 01:49, Stefano Stabellini wrote:
> On Fri, 23 Feb 2018, Julien Grall wrote:
>> Hi all,
>>
>> Arm has recently published a SMC Calling Convention (SMCCC)
>> specification update [1] that provides an optimised calling convention
>> and optional, discoverable support for mitigating CV
Hi,
On 13/02/18 14:31, Julien Grall wrote:
> Hi,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> Processing maintenance interrupts and accessing the list registers
>> are dependent on the host's GIC version.
>> Introduce vgic-v2.c to contain GICv2 specific f
Hi,
forgot to mention:
On 13/02/18 14:31, Julien Grall wrote:
> Hi,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> Processing maintenance interrupts and accessing the list registers
>> are dependent on the host's GIC version.
>> Introduce vgic-v2.c to
Hi,
On 13/02/18 16:35, Julien Grall wrote:
> Hi,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> Tell Xen whether a particular VCPU has an IRQ that needs handling
>> in the guest. This is used to decide whether a VCPU is runnable.
>>
>> This is based on Linux com
Hi,
On 26/02/18 16:02, Julien Grall wrote:
> Hi Andre,
>
> On 02/26/2018 03:13 PM, Andre Przywara wrote:
>> Hi,
>>
>> On 13/02/18 14:31, Julien Grall wrote:
>>> Hi,
>>>
>>> On 09/02/18 14:39, Andre Przywara wrote:
>>>> Processin
Hi,
On 26/02/18 15:59, Julien Grall wrote:
>
>
> On 02/26/2018 03:16 PM, Andre Przywara wrote:
>> Hi,
>
> Hi,
>
>> forgot to mention:
>>
>> On 13/02/18 14:31, Julien Grall wrote:
>>> Hi,
>>>
>>> On 09/02/18 14:39, Andre Prz
Hi,
On 26/02/18 15:55, Julien Grall wrote:
> Hi,
>
> On 02/26/2018 03:29 PM, Andre Przywara wrote:
>> On 13/02/18 16:35, Julien Grall wrote:
>>>> diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
>>>> index f4f2a04a60..9e7fb1edcb 100
Hi,
On 23/02/18 18:14, Julien Grall wrote:
>
>
> On 23/02/18 18:02, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 19/02/18 12:19, Julien Grall wrote:
>>> Hi,
>>>
>>> On 09/02/18 14:39, Andre Przywara wrote:
>>>>
Hi,
On 19/02/18 12:26, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> When we dump guest state on the Xen console, we also print the state of
>> IRQs that are on a VCPU.
>> Add the code to dump the state of an IRQ handled by the ne
Hi,
On 26/02/18 16:57, Julien Grall wrote:
>
>
> On 02/26/2018 04:48 PM, Andre Przywara wrote:
>> Hi,
>>
>> On 23/02/18 18:14, Julien Grall wrote:
>>>
>>>
>>> On 23/02/18 18:02, Andre Przywara wrote:
>>>> Hi,
>>
Hi,
On 19/02/18 12:39, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> This patch implements the function which is called by Xen when it wants
>> to register the virtual GIC.
>>
>> Signed-off-by: Andre Przywara
>> ---
Hi,
On 12/02/18 18:59, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> Provide a vgic_queue_irq_unlock() function which decides whether a
>> given IRQ needs to be queued to a VCPU's ap_list.
>> This should be called whenever a
Hi,
On 19/02/18 14:13, Julien Grall wrote:
>
>
> On 19/02/18 12:41, Andre Przywara wrote:
>> Hi,
>
> Hi,
>
>> On 16/02/18 16:57, Julien Grall wrote:
>>> On 09/02/18 14:39, Andre Przywara wrote:
>>>> + spin_lock
Hi,
On 19/02/18 12:34, Julien Grall wrote:
> Hi,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> The Xen core code requires an interrupt controller emulation to implement
>> arch_move_irqs(), to move the affinity of an hardware mapped virtual IRQ
>> to another c
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