Hi,
On 20/03/18 03:13, Julien Grall wrote:
> Hi Andre,
>
> On 03/15/2018 08:30 PM, Andre Przywara wrote:
>> diff --git a/xen/arch/arm/vgic/Makefile b/xen/arch/arm/vgic/Makefile
>> new file mode 100644
>> index 00..806826948e
>> --- /dev/null
>> +++
Hi,
On 20/03/18 01:17, Julien Grall wrote:
> Hi Andre,
>
> On 03/15/2018 08:30 PM, Andre Przywara wrote:
>> diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
>> index 002fec57e6..4b9664f313 100644
>> --- a/xen/arch/arm/vgic/vgic.c
>> +++ b/xen/
ts in write_lr that was mistakenly
> speaking about the read lr path.
I could indeed reproduce this today, though it interestingly didn't fire
in my testing when sending out v2. Weird.
The patch looks fine to me, I actually included it in my new series.
> Signed-off-by: Julien Grall
state of
an associated hardware IRQ.
This takes care of properly setting the _IRQ_INPROGRESS bit.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- rework setting _IRQ_INPROGRESS bit:
- no change when changing active state
- unconditional set/clear on changing pending state
- drop
Reviewed-by: Andre Przywara
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v2.c | 15 ---
xen/arch/arm/gic-v3.c | 13 -
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 7dfe6fc68d..aa0fc6c1a1 100644
t CPU bits in SGI injection handler
Andre Przywara (38):
ARM: GIC: add GIC_INVALID to enum gic_version
ARM: GIC: Allow tweaking the active and pending state of an IRQ
ARM: GIC: Allow reading pending state of a hardware IRQ
ARM: timer: Handle level triggered IRQs correctly
ARM: evtchn: Ha
Tell Xen whether a particular VCPU has an IRQ that needs handling
in the guest. This is used to decide whether a VCPU is runnable or
if a hypercall should be preempted to let the guest handle the IRQ.
This is based on Linux commit 90eee56c5f90, written by Eric Auger.
Signed-off-by: Andre
re is added in the
following patches.
This is based on Linux commit 0919e84c0fc1, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- replace "true" instead of "1" for the boolean parameter
Changelog v1 ... v2:
- make functions void
- do underflo
patch.
This is based on Linux commit 81eeb95ddbab, written by Christoffer Dall.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/vgic/vgic.c | 226 +++
xen/arch/arm/vgic/vgic.h | 10 +++
2 files changed, 236 insertions(+)
diff --
Marc Zyngier.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/vgic/vgic-mmio.c | 180 ++
xen/arch/arm/vgic/vgic-mmio.h | 89 +
2 files changed, 269 insertions(+)
create mode 100644 xen/arch/arm/vgic/vgic-mmio.c
c
interrupts and SPIs, but handles the ref-counting for LPIs.
This is based on Linux commit 64a959d66e47, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- extend comments to note preliminary nature of vgic_get_lpi()
Changelog v1 ... v2:
- reorder header file
The config register handlers are shared between the v2 and v3 emulation,
so their implementation goes into vgic-mmio.c, to be easily referenced
from the v3 emulation as well later.
This is based on Linux commit 79717e4ac09c, written by Andre Przywara.
Signed-off-by: Andre Przywara
Reviewed-by
triggered vIRQs, really, so
we need to add new functionality to re-sample the interrupt state.
Do this only when the new VGIC is in use.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- move vtimer_sync() from time.c into vtimer.c
- rename function to vtimer_update_irqs()
- refactor
The emulated ARM SBSA UART is using level triggered IRQ semantics,
however the current VGIC can only handle edge triggered IRQs, really.
Disable the existing workaround for this problem in case we have the
new VGIC in place, which can properly handle level triggered IRQs.
Signed-off-by: Andre
revision).
When the guest enables the distributor, we kick all VCPUs to get
potentially pending interrupts serviced.
This is based on Linux commit 2b0cda878965, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- fix misleading comment about PRODUCT_ID letter
- clarify on
e and add it to the Makefile.
This is from Linux' lib/list_sort.c, as of commit e327fd7c8667
("lib: add module support to linked list sorting tests").
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- introduce promptless Kconfig
- add Makefile line
- note Linux commit ID
.
Because the existing locking order between vgic_irq->irq_lock and
irq_desc->lock dictates so, we drop the irq_lock and retake them in the
proper order.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
Changelog v2 ... v3:
- fix indentation
- fix wording in comment
- add Revie
physical world.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/vgic/vgic.c | 71
1 file changed, 71 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index 90041eb071..07866d7243 100644
--- a/xen
, so chances are we are tasked to clear bits that are already zero.
Add a simple check to avoid pointless warnings in this case.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +-
xen/arch/arm/vgic/vgic-mmio.c| 91
The priority register handlers are shared between the v2 and v3 emulation,
so their implementation goes into vgic-mmio.c, to be easily referenced
from the v3 emulation as well later.
This is based on Linux commit 055658bf48fc, written by Andre Przywara.
Signed-off-by: Andre Przywara
Reviewed-by
to avoid touching all the users.
This is based on Linux commit b18b57787f5e, written by Christoffer Dall.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/include/asm-arm/new_vgic.h | 198 +
xen/include/asm-arm/vgic.h | 6 ++
2 files
As this register is v2 specific, its implementation lives entirely
in vgic-mmio-v2.c.
This register allows setting the source mask of an IPI.
This is based on Linux commit ed40213ef9b0, written by Andre Przywara.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/vgic
The Xen core/arch code relies on two abstracted functions to inject an
event channel IRQ and to query its pending state.
Implement those to query the state of the new VGIC implementation.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen/arch/arm/vgic/vgic.c | 23
on Linux commit fb848db39661, written by Andre Przywara.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 83
xen/arch/arm/vgic/vgic-mmio.c| 25
xen/arch/arm/vgic/vgic-mmio.h| 2 +
xen
there is no real technical
reason this struct has to fit in one page, so lifting the limit to two
pages seems like the most pragmatic solution.
Restrict this to compiling with the new VGIC and for ARM64 only.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- rework alloc_vcpu_struct() to
n the moment this is restricted to a vGIC-v2. To make the build system
happy, we provide a temporary dummy implementation of
vgic_v3_setup_hw() to allow building for now.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- fix indentation of Kconfig entry
- select NEEDS_LIST_SORT
- drop uncon
combine it with the
device's level to get the actual pending state.
Hardware mapped IRQs need some special handling, as their hardware state
has to be coordinated with the virtual pending bit to avoid hanging
or masked interrupts.
This is based on Linux commit 96b298000db4, written by Andre Prz
Triggering an IPI via this register is v2 specific, so the
implementation lives entirely in vgic-mmio-v2.c.
This is based on Linux commit 55cc01fb9004, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- fix target mask calculation
Changelog v1 ... v2:
- remove
The Xen arch code traps system registers writes from the guest and will
relay anything GIC related to the VGIC.
Since this affects only GICv3 (which we don't yet emulate), provide a
stub implementation of vgic_emulate() for now.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen
The ARM arch code requires an interrupt controller emulation to implement
vgic_clear_pending_irqs(), although it is suspected that it is actually
not necessary. Go with a stub for now to make the linker happy.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/vgic/vgic.c
When we dump guest state on the Xen console, we also print the state of
IRQs that are on a VCPU.
Add the code to dump the state of an IRQ handled by the new VGIC.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen/arch/arm/vgic/vgic.c | 25 +
1 file changed
pending state of a
particular interrupt. Due to hardware limitations this only works for
private interrupts of the current CPU, so there is no CPU field in the
prototype.
This adds gicv2/3_peek_irq() helper functions, to read a bit in a bitmap
spread over several MMIO registers.
Signed-off-by: Andre
evtchn_upcall_pending variable to make the interrupt
line match its status, and call this function upon every hypervisor
entry.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/domain.c | 7 +++
xen/arch/arm/traps.c| 1 +
xen/include/asm-arm/event.h | 1 +
3
-by: Andre Przywara
Acked-by: Julien Grall
---
xen/arch/arm/vgic/vgic-v2.c | 66 +
xen/arch/arm/vgic/vgic.h| 1 +
2 files changed, 67 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c
index ce77e58857..5516a8534f
a new first member: GIC_INVALID. Also make it obvious that this has a
"0" encoding.
Signed-off-by: Andre Przywara
---
xen/include/asm-arm/gic.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 565b0875ca..3079387e06 100644
setup the host GIC addresses.
This is based on Linux commit 140b086dd197, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- remove no longer needed asm/io.h header
- replace 0/1 with false/true for bool's
- clear _IRQ_INPROGRESS bit when retiring hardware mapped
Adds the sorting function to cover the case where you have more IRQs
to consider than you have LRs. We consider their priorities.
This uses the new sort_list() implementation imported from Linux.
This is based on Linux commit 8e4447457965, written by Christoffer Dall.
Signed-off-by: Andre
Enable the VGIC operation by properly initialising the registers
in the hypervisor GIC interface.
This is based on Linux commit f7b6985cc3d0, written by Eric Auger.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
Changelog v2 ... v3:
- replace "1" with "true"
initialize the VGIC.
Their prototypes are already in existing header files.
This is based on Linux commit ad275b8bb1e6, written by Eric Auger.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- move ROUNDUP(nr_spis) call before boundary check
Changelog v1 ... v2:
- remove stray kvm_
When a VCPU moves to another CPU, we need to adjust the target affinity
of any hardware mapped vIRQs, to observe our "physical-follows-virtual"
policy.
Implement arch_move_irqs() to adjust the physical affinity of all hardware
mapped vIRQs targetting this VCPU.
Signed-off-by: Andr
a hardware mapped vIRQ on the way.
This is based on Linux commit 2c234d6f1826, written by Andre Przywara.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 59 +++-
1 file changed, 58 insertions(+), 1 deletion
eturn some maximum value if
the VGIC has not been initialised yet.
Signed-off-by: Andre Przywara
---
Changelog v2 ... v3:
- drop premature #ifdef CONFIG_HAS_GICV3
- use new GIC_INVALID to detect uninitialised VGIC
xen/arch/arm/vgic/vgic-init.c | 60 +++
xe
can't
easily reuse the existing implementation.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen/arch/arm/vgic/vgic.c | 44
1 file changed, 44 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index 3d818
Hi,
On 22/03/18 08:16, Julien Grall wrote:
> Hi Andre,
>
> On 03/21/2018 04:32 PM, Andre Przywara wrote:
>> diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
>> index 131358a5a1..22c70ff7cd 100644
>> --- a/xen/arch/arm/vgic/vgic.c
>> +++ b/xen/
e. Please let me know if it's me not being smart enough
here instead ;-)
Signed-off-by: Andre Przywara
---
Hi,
will send a proper, merged v3a version of the patch separately.
Cheers,
Andre
xen/arch/arm/vgic/vgic-v2.c | 43 ++-
1 file changed, 30 inse
Hi,
On 22/03/18 01:51, Julien Grall wrote:
> Hi Andre,
>
> On 03/21/2018 04:31 PM, Andre Przywara wrote:
>> When playing around with hardware mapped, level triggered virtual IRQs,
>> there is the need to explicitly set the active or pending state of an
>> interrupt a
Hi,
On 22/03/18 03:52, Julien Grall wrote:
> Hi Andre,
>
> On 03/21/2018 04:32 PM, Andre Przywara wrote:
>> Tell Xen whether a particular VCPU has an IRQ that needs handling
>> in the guest. This is used to decide whether a VCPU is runnable or
>> if a hypercall sho
Hi,
On 22/03/18 08:00, Julien Grall wrote:
> Hi Andre,
>
> On 03/21/2018 04:32 PM, Andre Przywara wrote:
>> This patch implements the function which is called by Xen when it wants
>> to register the virtual GIC.
>> This also implements vgic_max_vcpus() for the new VGIC
Hi,
this is just an update of the three patches which didn't get any review
tags so far.
The fixes for the new versions of 03/39 and 39/39 are pretty straight
forward, but 14/39 is more of a beast. I sent a diff to the original
patch [1] separately to give an idea of the changes.
I added the R-b:
n the moment this is restricted to a vGIC-v2. To make the build system
happy, we provide a temporary dummy implementation of
vgic_v3_setup_hw() to allow building for now.
Signed-off-by: Andre Przywara
---
Changelog v3 ... v3a:
- print panic when trying to run on GICv3 hardware
Changelog v2 ... v3:
state of
an associated hardware IRQ.
This takes care of properly setting the _IRQ_INPROGRESS bit.
Signed-off-by: Andre Przywara
---
Changelog v3 ... v3a:
- always set/clear _IRQ_INPROGRESS bit (not only for guest IRQs)
- add comments
Changelog v2 ... v3:
- extend comments to note preliminary nature
setup the host GIC addresses.
This is based on Linux commit 140b086dd197, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog v3 ... v3a:
- take hardware IRQ lock in vgic_v2_fold_lr_state()
- fix last remaining u32 usage
- print message when using new VGIC
- add TODO about
Hi,
On 22/03/18 14:06, Julien Grall wrote:
> Hi Andre,
>
> On 03/22/2018 11:56 AM, Andre Przywara wrote:
>> + /* The locking order forces us to drop and re-take the locks
>> here. */
>> + if ( irq->hw )
>> + {
>&g
Hi,
On 22/03/18 14:06, Julien Grall wrote:
> Hi Andre,
>
> On 03/22/2018 11:56 AM, Andre Przywara wrote:
>> + /* The locking order forces us to drop and re-take the locks
>> here. */
>> + if ( irq->hw )
>> + {
>&g
Hi,
On 26/03/18 21:28, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> The ARM Generic Timer uses a level-sensitive interrupt semantic. We
>> easily catch when the line goes high, as this triggers the hardware IRQ.
>> However we also have to keep t
Hi,
On 26/03/18 22:30, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> Implement the framework for syncing IRQs between our emulation and the
>> list registers, which represent the guest's view of IRQs.
>> This is done in vgic_sync_from_
Hi,
On 27/03/18 00:22, Stefano Stabellini wrote:
> On Thu, 22 Mar 2018, Andre Przywara wrote:
>> Processing maintenance interrupts and accessing the list registers
>> are dependent on the host's GIC version.
>> Introduce vgic-v2.c to contain GICv2 specific functio
Hi,
On 27/03/18 22:06, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> As the enable register handlers are shared between the v2 and v3
>> emulation, their implementation goes into vgic-mmio.c, to be easily
>> referenced from the v3 emulation a
Hi,
On 27/03/18 23:38, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> To find an unused virtual IRQ number Xen uses a scheme to track used
>> virtual IRQs.
>> Implement this interface in the new VGIC to make the Xen core/arch code
>> happy.
&
Hi,
On 27/03/18 21:07, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> Add an MMIO handling framework to the VGIC emulation:
>> Each register is described by its offset, size (or number of bits per
>> IRQ, if applicable) and the read/write handler
Hi,
On 27/03/18 23:27, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> As this register is v2 specific, its implementation lives entirely
>> in vgic-mmio-v2.c.
>> This register allows setting the source mask of an IPI.
>>
>> This is b
Hi,
On 27/03/18 21:38, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> Those three registers are v2 emulation specific, so their implementation
>> lives entirely in vgic-mmio-v2.c. Also they are handled in one function,
>> as their implementation is
Hi,
On 28/03/18 00:16, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> This patch allocates and initializes the data structures used to model
>> the vgic distributor and virtual cpu interfaces. At that stage the
>> number of IRQs and number of v
Hi,
On 27/03/18 22:14, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> The pending register handlers are shared between the v2 and v3
>> emulation, so their implementation goes into vgic-mmio.c, to be easily
>> referenced from the v3 emulation as wel
Hi,
On 28/03/18 01:01, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> The event channel IRQ has level triggered semantics, however the current
>> VGIC treats everything as edge triggered.
>> To correctly process those IRQs, we have to lower the (vi
Hi,
On 28/03/18 18:46, Stefano Stabellini wrote:
> On Wed, 28 Mar 2018, Andre Przywara wrote:
>> On 28/03/18 01:01, Stefano Stabellini wrote:
>>> On Wed, 21 Mar 2018, Andre Przywara wrote:
>>>> The event channel IRQ has level triggered semantics, however the current
Hi,
On 28/03/18 19:47, Stefano Stabellini wrote:
> On Wed, 21 Mar 2018, Andre Przywara wrote:
>> When a VCPU moves to another CPU, we need to adjust the target affinity
>> of any hardware mapped vIRQs, to observe our "physical-follows-virtual"
>> policy.
>>
ject the interrupt. The second call is then a
NOP.
Signed-off-by: Andre Przywara
---
Hi,
this would ideally have been part of a former patch:
"[PATCH v3 06/39] ARM: evtchn: Handle level triggered IRQs correctly",
but this has been merged already, so this has to be a follow-up.
Ide
Hi,
On 25/05/18 06:32, Oleksandr Andrushchenko wrote:
> On 05/23/2018 02:46 PM, Juergen Gross wrote:
>> On 23/05/18 13:36, Oleksandr Andrushchenko wrote:
>>> From: Oleksandr Andrushchenko
>>>
>>> Building for a 32-bit target results in warnings from casting
>>> between a 32-bit pointer and a 64-b
Hi,
On 04/09/18 18:25, Amit Singh Tomar wrote:
> This patch adds image size and flags to XEN image header. It uses
> those fields according to the updated Linux kernel image definition.
>
> With this patch bootloader can now place XEN image anywhere in system
> RAM at 2MB aligned address without
Hi,
On 05/09/18 13:52, Amit Tomer wrote:
> Hello,
>
> Thanks for having a look.
>
> On Wed, Sep 5, 2018 at 6:07 PM Andre Przywara wrote:
>>
>> Hi,
>>
>> I don't think it's helpful to hide that KERNEL_SIZE definition in
>> another file. Ple
aligned address without to worry about relocation.
> For instance, it fixes the XEN boot on Amlogic SoC where bootloader(U-BOOT)
> always relocates the XEN image to an address range reserved for firmware data.
>
> Signed-off-by: Amit Singh Tomar
Thanks, looks good to me now:
Reviewed-
On Tue, 9 Oct 2018 09:58:14 +0100
Peter Maydell wrote:
Hi,
> On 8 October 2018 at 19:00, Julien Grall wrote:
> > Per the Linux arm64 booting protocol [1], the load offset can
> > definitely be 0. The bootloader (here QEMU) should not assume a
> > specific text offset, Linux actually provides an
sses for Dom0 are identical to those from the hardware.
The mainline kernel DT for the Espressobin board with an Marvell 3720 SoC
has the GIC in such an translated bus, so this patch allows this board
to boot properly (after adding support for the SoC's UART).
Signed-off-by: Andre Przywa
Hi,
Yeah! Locking discussions! Have fun below ;-)
On 30/01/18 13:19, Julien Grall wrote:
> Hi Andre,
>
> On 24/01/18 18:10, Andre Przywara wrote:
>> At the moment we happily access VGIC internal data structures like
>> the rank and struct pending_irq in gic.c, which sh
Hi,
On 31/01/18 16:16, Julien Grall wrote:
> Hi,
>
> On 24/01/18 18:10, Andre Przywara wrote:
>> At the moment we happily access the VGIC internal struct pending_irq
>> (which describes a virtual IRQ) in irq.c.
>> Factor out the actually needed functionality to learn
Hi,
On 31/01/18 16:30, Julien Grall wrote:
>
>
> On 31/01/18 15:54, Andre Przywara wrote:
>> Hi,
>>
>> Yeah! Locking discussions! Have fun below ;-)
>>
>> On 30/01/18 13:19, Julien Grall wrote:
>>> Hi Andre,
>>>
>>> On 24/01/18
Hi,
On 30/01/18 14:36, Roger Pau Monné wrote:
> On Wed, Jan 24, 2018 at 06:10:58PM +0000, Andre Przywara wrote:
>> On ARM the maximum number of IRQs is a constant, but we share it being
>> a variable to match x86. Since we are not supposed to alter it, let's
>> m
Hi,
On 01/02/18 13:47, Julien Grall wrote:
> Hi Andre,
>
> On 01/02/18 13:43, Andre Przywara wrote:
>> On 30/01/18 14:36, Roger Pau Monné wrote:
>>> On Wed, Jan 24, 2018 at 06:10:58PM +, Andre Przywara wrote:
>>>> On ARM the maximum number of IRQs is a co
Hi,
On 01/02/18 13:57, Roger Pau Monné wrote:
> On Thu, Feb 01, 2018 at 01:43:09PM +0000, Andre Przywara wrote:
>> Hi,
>>
>> On 30/01/18 14:36, Roger Pau Monné wrote:
>>> On Wed, Jan 24, 2018 at 06:10:58PM +, Andre Przywara wrote:
>>>> On ARM the ma
Hi,
On 01/02/18 14:39, Julien Grall wrote:
>
>
> On 01/02/18 14:34, Andre Przywara wrote:
>> Hi,
>
> Hi,
>
>> On 01/02/18 13:47, Julien Grall wrote:
>>> Hi Andre,
>>>
>>> On 01/02/18 13:43, Andre Przywara wrote:
>>>> On 30
alk because the instruction
> syndrome will always be invalid (see B3-1433 in DDI 0406C.c and
> D10-2460 in DDI 0487C.a).
Yes, that looks correct to me.
> Signed-off-by: Julien Grall
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
>
mmio_info_t *info)
> {
> const struct hsr_dabt dabt = info->dabt;
> struct cpu_user_regs *regs = guest_cpu_user_regs();
> +int ret;
>
> -return handler->ops->write(v, info, get_user_reg(regs, dabt.reg),
> - handler->pri
do.
Very nice!
> Signed-off-by: Julien Grall
> Reviewed-by: Stefano Stabellini
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> Changes in v2
> - Add Stefano's reviewed-by
> ---
> xen/arch/arm/vgic-v2.c | 2 --
> xen/arch/arm/vgic-v3-its
Hi,
On 02/02/18 10:14, Julien Grall wrote:
> domain_crash_synchronous() should only be used when something went wrong
> in Xen. It is better to inject to the guest as it will be in a better
> position to provide helpful information (stack trace...).
>
> Signed-off-by: Julien Grall
> Reviewed-by:
Hi,
On 02/02/18 14:47, Julien Grall wrote:
>
>
> On 02/02/18 14:34, Andre Przywara wrote:
>> Hi,
>
> Hi,
>
>> On 02/02/18 10:14, Julien Grall wrote:
>>> At the moment, try_handle_mmio() will do check on the HSR and bail out
>>> if one check fa
Hi,
On 02/02/18 23:10, Julien Grall wrote:
>
>
> On 02/02/2018 22:48, Stefano Stabellini wrote:
>> Committed, thanks
>
> I know you acked/reviewed all the patches, but it would have been nice
> to wait/give more feedback regarding Andre's valid point on patch #4.
I think that's fine. I didn't
On ARM the maximum number of IRQs is a constant, but we share it being
a variable to match x86. Since we are not supposed to alter it, let's
mark it as "const" to avoid accidental change.
Suggested-by: Julien Grall
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen
The functions to actually populate a list register were accessing
the VGIC internal pending_irq struct, although they should be abstracting
from that.
Break the needed information down to remove the reference to pending_irq
from gic-v[23].c.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano
At the moment we happily access the VGIC internal struct pending_irq
(which describes a virtual IRQ) in irq.c.
Factor out the actually needed functionality to learn the associated
hardware IRQ and move that into gic-vgic.c to improve abstraction.
Signed-off-by: Andre Przywara
Acked-by: Stefano
said accesses to VGIC data structures and improves abstraction.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-vgic.c| 36
xen/arch/arm/gic.c | 44 ++--
xen/include/asm-arm/vgic.h | 2 ++
3 files changed
least for non-ITS code. The ITS is a beast own its own
(blame the author) and will be addressed later.
Andre Przywara (8):
ARM: VGIC: drop unneeded gic_restore_pending_irqs()
ARM: VGIC: split gic.c to observe hardware/virtual GIC separation
ARM: VGIC: split up gic_dump_info() to cover virtua
separate file,
so that gic.c does what it says on the tin.
Signed-off-by: Andre Przywara
---
xen/arch/arm/Makefile | 1 +
xen/arch/arm/gic-vgic.c | 396 ++
xen/arch/arm/gic.c| 363 +-
xen/include/asm-arm
Currently gic_dump_info() not only dumps the hardware state of the GIC,
but also the VGIC internal virtual IRQ lists.
Split the latter off and move it into gic-vgic.c to observe the abstraction.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano Stabellini
---
xen/arch/arm/domain.c | 1
needed, since we will always call gic_inject() anyway.
So remove that call (and the forward declaration) to streamline this
interface and make separating the GIC from the VGIC world later.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
Reviewed-by: Stefano Stabellini
---
xen/arch/arm
In event.h we very deeply dive into the VGIC to learn if an event for
a guest is pending.
Rework that function to abstract the VGIC specific part out. Also
reorder the queries there, as we only actually need to check for the
event channel if there are no other pending IRQs.
Signed-off-by: Andre
Hi,
On 06/02/18 14:21, Julien Grall wrote:
> Hi Andre,
>
> On 02/05/2018 04:19 PM, Andre Przywara wrote:
>> At the moment we happily access VGIC internal data structures like
>> the rank and struct pending_irq in gic.c, which should be VGIC agnostic.
>>
&
Currently gic_dump_info() not only dumps the hardware state of the GIC,
but also the VGIC internal virtual IRQ lists.
Split the latter off and move it into gic-vgic.c to observe the abstraction.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano Stabellini
---
xen/arch/arm/domain.c | 1
At the moment we happily access the VGIC internal struct pending_irq
(which describes a virtual IRQ) in irq.c.
Factor out the actually needed functionality to learn the associated
hardware IRQ and move that into gic-vgic.c to improve abstraction.
Signed-off-by: Andre Przywara
Acked-by: Stefano
In event.h we very deeply dive into the VGIC to learn if an event for
a guest is pending.
Rework that function to abstract the VGIC specific part out. Also
reorder the queries there, as we only actually need to check for the
event channel if there are no other pending IRQs.
Signed-off-by: Andre
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