The Xen arch code traps system registers writes from the guest and will
relay anything GIC related to the VGIC.
Since this affects only GICv3 (which we don't yet emulate), provide a
stub implementation of vgic_emulate() for now.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
27;s GICv3
emulation.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
Changelog RFC ... v1:
- Add Julien's ACK
xen/arch/arm/gic-v3.c | 4
xen/arch/arm/vgic-v3.c | 14 ++
2 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xe
actually deal with.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- extend commit message
xen/arch/arm/gic-v2.c | 2 +-
xen/include/asm-arm/gic.h | 18 --
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
The prototype for gic_remove_from_lr_pending() is the last function in
gic.h which references a VGIC data structure.
Move it over to vgic.h, so that we can remove the inclusion of vgic.h
from gic.h. We add it to asm/domain.h instead, where it is actually
needed.
Signed-off-by: Andre Przywara
The macro formerly named LOG_2 has been recently renamed to ilog2,
so adjust the name in vgic-mmio.h.
Signed-off-by: Andre Przywara
---
Hi,
I somehow rebased without actually trying to re-compile (since the rebase
itself went through smoothly). So I missed this subtle renaming in the tree
Hi,
On 05/03/18 16:03, Andre Przywara wrote:
> tl;dr: Coarse changelog below, individual patches have changelogs as
> well.
>
> This is an updated version of the new VGIC-v2 implementation.
For the brave amongst you who actually want to try it, there is a git
repo with these patch
Hi,
On 06/03/18 15:46, Julien Grall wrote:
> Hi Andre,
>
> On 05/03/18 16:03, Andre Przywara wrote:
>> The bit definition for the CPUID mask in the GICv2 LR register was
>> wrong, fortunately the current implementation does not use that bit.
>> Fix it up (it's st
Hi,
On 06/03/18 17:46, Julien Grall wrote:
> Hi Andre,
>
> On 05/03/18 16:03, Andre Przywara wrote:
>> Add a new header file for the new and improved GIC implementation.
>> The big change is that we now have a struct vgic_irq per IRQ instead
>> of spreading all t
Hi,
On 07/03/18 11:02, Julien Grall wrote:
> Hi Andre,
>
> Overall this patch looks good. Few comments below.
>
> On 03/05/2018 04:03 PM, Andre Przywara wrote:
>> +/*
>> + * Only valid injection if changing level for level-triggered IRQs or
>> for a
>> +
Hi,
On 07/03/18 11:47, Julien Grall wrote:
> Hi Andre,
>
> On 03/05/2018 04:03 PM, Andre Przywara wrote:
>> Implement the framework for syncing IRQs between our emulation and the
>> list registers, which represent the guest's view of IRQs.
>> This is do
Hi,
On 07/03/18 12:10, Julien Grall wrote:
> Hi Andre,
>
> On 03/05/2018 04:03 PM, Andre Przywara wrote:
>> +void vgic_v2_fold_lr_state(struct vcpu *vcpu)
>> +{
>> + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
>> + unsigned int used_lrs = vcpu-&g
Hi,
On 07/03/18 17:01, Julien Grall wrote:
> Hi Andre,
>
> On 03/05/2018 04:03 PM, Andre Przywara wrote:
>> As the enable register handlers are shared between the v2 and v3
>> emulation, their implementation goes into vgic-mmio.c, to be easily
>> referenced from the
Hi,
On 06/03/18 13:49, Julien Grall wrote:
>
>
> On 05/03/18 17:08, Julien Grall wrote:
>> On 05/03/18 16:03, Andre Przywara wrote:
>>> Instead of hard coding the architected redistributor stride into the
>>> code, lets use a clear #define to the two values fo
Hi,
On 08/03/18 15:48, Julien Grall wrote:
>
>
> On 05/03/18 16:03, Andre Przywara wrote:
>> The priority register handlers are shared between the v2 and v3
>> emulation,
>> so their implementation goes into vgic-mmio.c, to be easily referenced
>> from the v3
Hi,
On 06/03/18 16:06, Julien Grall wrote:
> Hi Andre,
>
> On 05/03/18 16:03, Andre Przywara wrote:
>> So far our LR read/write functions do not handle the EOI bit and the
>> source CPUID bits in an LR, because the current VGIC implementation does
>> not use them
Hi,
On 08/03/18 16:18, Julien Grall wrote:
> Hi Andre,
>
> On 05/03/18 16:04, Andre Przywara wrote:
>> The target register handlers are v2 emulation specific, so their
>> implementation lives entirely in vgic-mmio-v2.c.
>> We copy the old VGIC behaviour of assigni
Hi,
On 09/03/18 10:38, awokd wrote:
> On Fri, March 9, 2018 10:03 am, Andrew Cooper wrote:
>> On 09/03/2018 09:37, awokd wrote:
>
>>
>> Xen currently has x86 and ARM as supported architectures, so there is a
>> reasonable split between common and arch-specific code. As a start, you'd
>> need to
The prototype for gic_remove_from_lr_pending() is the last function in
gic.h which references a VGIC data structure.
Move it over to vgic.h, so that we can remove the inclusion of vgic.h
from gic.h. We add it to asm/domain.h instead, where it is actually
needed.
Signed-off-by: Andre Przywara
with those patches is available at the new-vgic/prep branch at:
git://linux-arm.org/xen-ap.git
http://www.linux-arm.org/git?p=xen-ap.git;a=shortlog;h=refs/heads/vgic-new/prep
Cheers,
Andre
Andre Przywara (17):
ARM: vGICv3: clarify on GUEST_GICV3_RDIST_REGIONS symbol
ARM: GICv3: use hardware GICv3 red
structures.
Move the actual functionality into vgic.c, and provide a shim in
domain.h, to keep this VGIC internal.
Signed-off-by: Andre Przywara
---
Changelog:
- rename helper function and wrap in domain.h
xen/arch/arm/domain.c| 14 --
xen/arch/arm/vgic.c | 14
value.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen/arch/arm/gic-v3.c | 3 +--
xen/arch/arm/vgic-v3.c| 14 --
xen/include/asm-arm/domain.h | 1 -
xen/include/asm-arm/vgic.h| 1 -
xen/include/public/arch-arm.h | 1 -
5 files changed, 1 inse
gic_event_needs_delivery() is not named very intuitively, especially
the gic_ prefix is somewhat misleading.
Rename it to vgic_pending_irq(), which makes it clear that this relates
to the virtual GIC and is about interrupts.
Signed-off-by: Andre Przywara
---
Changelog:
- Add vcpu parameter
Normally there is only one GICv3 redistributor region, and we use
that for DomU guests using a GICv3.
Explain the background in a comment and why we need to keep the number
of hardware regions for Dom0.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen/arch/arm/vgic-v3.c | 12
The bit definition for the CPUID mask in the GICv2 LR register was
wrong, fortunately the current implementation does not use that bit.
Fix it up (it's starting at bit 10, not bit 9) and clean up some
nearby definitions on the way.
This will be used by the new VGIC shortly.
Signed-off-by:
dware domain.
This avoids the hardware GIC code to reference vGIC data structures.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/gic-v3.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
ity, using the already existing
vcpu_kick() prototype (used in x86 only so far), to make this available
to the rest of the Xen code.
Signed-off-by: Andre Przywara
---
- Rename to vcpu_kick(), to blend in with existing (x86) prototype
xen/arch/arm/domain.c | 12
xen/arch/arm/vgi
The two central functions to synchronise our emulated VGIC state with
the GIC hardware (the LRs, really), are named somewhat confusingly.
Rename them from gic_inject() to vgic_sync_to_lrs() and from
gic_clear_lrs() to vgic_sync_from_lrs(), to make the code more readable.
Signed-off-by: Andre
Currently vgic.h both contains prototypes used by Xen arch code outside
of the actual VGIC (for instance vgic_vcpu_inject_irq()), and prototypes
for functions used by the VGIC internally.
Group them to later allow an easy split with one #ifdef.
Signed-off-by: Andre Przywara
Reviewed-by: Julien
27;s GICv3
emulation.
Signed-off-by: Andre Przywara
---
Changelog:
- merge in GICV3_GICR_SIZE definition
xen/arch/arm/gic-v3.c | 4
xen/arch/arm/vgic-v3.c| 14 ++
xen/include/asm-arm/gic_v3_defs.h | 5 +
3 files changed, 11 insertions(+), 12 deletions(
: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/gic-v2.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 2b271ba322..fa9afc2be8 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -235,6
So far the number of list registers (LRs) a GIC implements is only
needed in the hardware facing side of the VGIC code (gic-vgic.c).
The new VGIC will need this information in more and multiple places, so
export a function that returns the number.
Signed-off-by: Andre Przywara
Reviewed-by
prepares the callers
to do the right thing later automatically.
Signed-off-by: Andre Przywara
---
Changelog:
- keep function as returning void
xen/arch/arm/domain.c | 4 ++--
xen/arch/arm/gic-v3-lpi.c | 2 +-
xen/arch/arm/irq.c | 2 +-
xen/arch/arm/time.c| 2 +-
heir usage in gic-v3.c
and is needed to allow co-existence of the GICv2 and GICv3 definitions
in the same file.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
xen/arch/arm/gic-v3.c | 48 +++---
xen/include/asm-ar
evaluates to 31.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/arch/arm/gic-v3.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 8b41704cf1..09b49a07d5 100644
--- a/xen/arch/arm/gic-v3.c
+++ b
definition of these
embedded structures into vgic.h, and just use the opaque type in the arch
specific structures.
This allows easy switching between different implementations later.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
xen/include/asm-arm/domain.h | 85
Hi,
On 09/03/18 18:18, Julien Grall wrote:
> Hi Andre,
>
> On 05/03/18 16:04, Andre Przywara wrote:
>> The ARM arch code requires an interrupt controller emulation to implement
>> vgic_clear_pending_irqs(), although it is suspected that it is actually
>> not necessary
Hi,
On 08/03/18 15:39, Julien Grall wrote:
> Hi Andre,
>
> On 05/03/18 16:03, Andre Przywara wrote:
>> The active register handlers are shared between the v2 and v3 emulation,
>> so their implementation goes into vgic-mmio.c, to be easily referenced
>> from the
Hi,
On 13/03/18 17:14, Julien Grall wrote:
> Hi Andre,
>
> On 13/03/18 17:02, Andre Przywara wrote:
>> On 08/03/18 15:39, Julien Grall wrote:
>>> On 05/03/18 16:03, Andre Przywara wrote:
>>>> +/*
>>>> + * We don't actually support clearing th
Hi,
On 13/03/18 17:42, Julien Grall wrote:
> Hi,
>
> On 13/03/18 17:34, Andre Przywara wrote:
>> On 13/03/18 17:14, Julien Grall wrote:
>>> On 13/03/18 17:02, Andre Przywara wrote:
>>>> On 08/03/18 15:39, Julien Grall wrote:
>>>>> On 05/03/18
On 09/03/18 17:35, julien.gr...@arm.com wrote:
> From: Julien Grall
>
> At the moment, write_lr is assuming the caller will set correctly the
> group. However the group should always be 0 when the guest is using
> vGICv2 and 1 for vGICv3. As the caller should not care about the group,
> override
Hi,
On 09/03/18 16:35, julien.gr...@arm.com wrote:
> From: Julien Grall
>
> hw_status can only be 1 or 0. So convert to a bool.
>
> Signed-off-by: Julien Grall
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> xen/arch/arm/gic-v2.c | 9 +
> xen/a
gt; @@ -209,7 +209,8 @@ struct gic_lr {
> /* Virtual IRQ */
> uint32_t virq;
> uint8_t priority;
> - uint8_t state;
> + bool active;
> + bool pending;
> bool hw_status;
> };
>
> diff --git a/xen/include/asm-arm/gic_v3_defs.h
> b/xen/include/asm-arm
ield (e.g eoi, source) that clashes with the PIRQ field.
Makes some sense, yes.
> Signed-off-by: Julien Grall
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> xen/arch/arm/gic-v2.c | 13 ++---
> xen/arch/arm/gic-v3.c | 10 +++---
> xen/include/asm-arm/
Hi,
On 09/03/18 16:35, julien.gr...@arm.com wrote:
> From: Andre Przywara
I think this is quite different from what I ever wrote, so please drop
my authorship here.
> So far our LR read/write functions do not handle the EOI bit and the
> source CPUID bits in an LR, because the cur
From: Julien Grall
hw_status can only be 1 or 0. So convert to a bool.
Signed-off-by: Julien Grall
Reviewed-by: Andre Przywara
Signed-off-by: Andre Przywara
---
Changes:
- Remove == *LR_HW as it is pointless
- Add Andre's reviewed-by
xen/arch/arm/gic-v2.c | 9 +
xen/arc
interrupts and SPIs, but handles the ref-counting for LPIs.
This is based on Linux commit 64a959d66e47, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- reorder header file inclusion
xen/arch/arm/vgic/vgic.c | 124
to avoid touching all the users.
This is based on Linux commit b18b57787f5e, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- define CONFIG_EDGE to false instead of using enum
- remove not needed forward declaration
- remove unneeded macros
- add emacs footer
From: Julien Grall
Mostly making the code nicer to read.
Signed-off-by: Julien Grall
Reviewed-by: Andre Przywara
Signed-off-by: Andre Przywara
---
Changes:
- Use 1ULL
- Remove pointless == *_STATE_*
xen/arch/arm/gic-v2.c | 15 +++
xen/arch/arm/gic-v3.c
re is added in the
following patches.
This is based on Linux commit 0919e84c0fc1, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- make functions void
- do underflow setting directly (no v2/v3 indirection)
- fix multiple SGIs injections (as the late Linux bugfix)
cesses
- use interface for HCR bit changes
- iterate over set CPU bits in SGI injection handler
Andre Przywara (39):
ARM: VGIC: rename gic_event_needs_delivery()
ARM: Implement vcpu_kick()
ARM: GIC: Allow tweaking the active and pending state of an IRQ
ARM: GIC: Allow reading pending state
ity, using the already existing
vcpu_kick() prototype (used in x86 only so far), to make this available
to the rest of the Xen code.
Also adjust the perfcounter name to reflect the new usage.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- use vcpu_kick() name from x86 and existing
From: Julien Grall
Signed-off-by: Julien Grall
Reviewed-by: Andre Przywara
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- Add Andre's reviewed-by
xen/arch/arm/gic-vgic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/gic-vgic.c b/xen/arc
on whether the vIRQ
has a corresponding pIRQ.
This allows the new VGIC to use this information.
This is based on the original patch sent by Andre Przywara [1].
[1] https://lists.xenproject.org/archives/html/xen-devel/2018-03/msg00435.html
Signed-off-by: Julien Grall
Reviewed-by: Andre Przywara
Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- adjust indentation
- remove unneeded macros
- use unsigned types
- use new ilog2() implementation
xen/arch/arm/vgic/vgic-mmio.c | 180 ++
xen/arch/arm/vgic/vgic-mmio.h
future. The current VGIC expect this to be the current VCPU, so add
an assert to spot any regressions.
Signed-off-by: Andre Przywara
---
Changelog v1 .. v2:
- rename to vgic_vcpu_pending_irq()
- add VCPU parameter
xen/arch/arm/gic
state of
an associated hardware IRQ.
This takes care of properly setting the _IRQ_INPROGRESS bit.
For this it adds gicv2/3_peek_irq() helper functions, to read a bit in a
bitmap spread over several MMIO registers.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- properly set _IRQ_INPROGRESS
evtchn_upcall_pending variable to make the interrupt
line match its status, and call this function upon every hypervisor
entry.
Signed-off-by: Andre Przywara
---
xen/arch/arm/domain.c | 7 +++
xen/arch/arm/traps.c| 1 +
xen/include/asm-arm/event.h | 1 +
3 files changed, 9 insertions
Reviewed-by: Andre Przywara
Signed-off-by: Andre Przywara
---
Changes:
- Add Andre's reviewed-by
xen/arch/arm/gic-v2.c | 13 ++---
xen/arch/arm/gic-v3.c | 10 +++---
xen/include/asm-arm/gic.h | 2 +-
3 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/xen/arch/ar
vGIC (and the LR).
The VGIC in Xen so far only implemented edge triggered vIRQs, really, so
we need to add new functionality to re-sample the interrupt state.
Do this only when the new VGIC is in use.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- restrict to new VGIC
- add TODO: comment
pending state of a
particular interrupt. Due to hardware limitations this only works for
private interrupts of the current CPU, so there is no CPU field in the
prototype.
This adds gicv2/3_peek_irq() helper functions, to read a bit in a bitmap
spread over several MMIO registers.
Signed-off-by: Andre
Adds the sorting function to cover the case where you have more IRQs
to consider than you have LRs. We consider their priorities.
This uses the new sort_list() implementation imported from Linux.
This is based on Linux commit 8e4447457965, written by Christoffer Dall.
Signed-off-by: Andre
Triggering an IPI via this register is v2 specific, so the
implementation lives entirely in vgic-mmio-v2.c.
This is based on Linux commit 55cc01fb9004, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- remove stray rebase artefact
xen/arch/arm/vgic/vgic-mmio
physical world.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
Changelog v1 ... v2:
- Add Reviewed-by:
xen/arch/arm/vgic/vgic.c | 71
1 file changed, 71 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index
patch.
This is based on Linux commit 81eeb95ddbab, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- rework validate_injection()
- add comments
- make vgic_inject_irq a void function
- fix comment
xen/arch/arm/vgic/vgic.c
like update_lr for the group.
Signed-off-by: Julien Grall
Reviewed-by: Andre Przywara
Signed-off-by: Andre Przywara
---
Changes:
- Add Andre's reviewed-by
xen/arch/arm/gic-v2.c | 4 +---
xen/arch/arm/gic-v3.c | 11 ---
xen/include/asm-arm/gic.h | 1 -
3 files chang
The emulated ARM SBSA UART is using level triggered IRQ semantics,
however the current VGIC can only handle edge triggered IRQs, really.
Disable the existing workaround for this problem in case we have the
new VGIC in place, which can properly handle level triggered IRQs.
Signed-off-by: Andre
This pulls in Linux' list_sort.c, which is a merge sort implementation
for linked lists. Apart from adding a full featured license header and
adjusting the #include file, nothing has been changed in this code.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- split out to just co
Tell Xen whether a particular VCPU has an IRQ that needs handling
in the guest. This is used to decide whether a VCPU is runnable or
if a hypercall should be preempted to let the guest handle the IRQ.
This is based on Linux commit 90eee56c5f90, written by Eric Auger.
Signed-off-by: Andre
a hardware mapped vIRQ on the way.
This is based on Linux commit 2c234d6f1826, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- directly update affinity (avoid vgic_sync_hardware_irq() and lock)
xen/arch/arm/vgic/vgic-mmio-v2.c | 59
This patch implements the function which is called by Xen when it wants
to register the virtual GIC.
This also implements vgic_max_vcpus() for the new VGIC, which reports
back the maximum number of VCPUs a certain GIC model supports.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic
The Xen core/arch code relies on two abstracted functions to inject an
event channel IRQ and to query its pending state.
Implement those to query the state of the new VGIC implementation.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
Changelog v1 ... v2:
- Add Acked-by:
xen/arch
Enable the VGIC operation by properly initialising the registers
in the hypervisor GIC interface.
This is based on Linux commit f7b6985cc3d0, written by Eric Auger.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- move patch from later part in the series
xen/arch/arm/vgic/vgic-v2.c
The priority register handlers are shared between the v2 and v3 emulation,
so their implementation goes into vgic-mmio.c, to be easily referenced
from the v3 emulation as well later.
This is based on Linux commit 055658bf48fc, written by Andre Przywara.
Signed-off-by: Andre Przywara
setup the host GIC addresses.
This is based on Linux commit 140b086dd197, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- remove v2 specific underflow function (now generic)
- re-add Linux code to properly handle acked level IRQs
xen/arch/arm/vgic/vgic-v2.c
initialize the VGIC.
Their prototypes are already in existing header files.
This is based on Linux commit ad275b8bb1e6, written by Eric Auger.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- remove stray kvm_ prefix in comment
- use unsigned int
- ROUNDUP number of SPIs
- fix
revision).
When the guest enables the distributor, we kick all VCPUs to get
potentially pending interrupts serviced.
This is based on Linux commit 2b0cda878965, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- use new IIDR values (KVM product ID, Xen revision)
- add
on Linux commit fb848db39661, written by Andre Przywara.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
Changelog v1 ... v2:
- Add Reviewed-by:
xen/arch/arm/vgic/vgic-mmio-v2.c | 83
xen/arch/arm/vgic/vgic-mmio.c| 25
xen
combine it with the
device's level to get the actual pending state.
Hardware mapped IRQs need some special handling, as their hardware state
has to be coordinated with the virtual pending bit to avoid hanging
or masked interrupts.
This is based on Linux commit 96b298000db4, written by Andre Prz
.
Because the existing locking order between vgic_irq->irq_lock and
irq_desc->lock dictates so, we drop the irq_lock and retake them in the
proper order.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- ASSERT on h/w IRQ and vIRQ staying in sync
xen/arch/arm/vgic/vgic-mmio-v2.c
, so chances are we are tasked to clear bits that are already zero.
Add a simple check to avoid pointless warnings in this case.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- print a line for every failing IRQ
xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +-
xen/arch/arm/vgic/vgic-mmio.c
n the moment this is restricted to a vGIC-v2. To make the build system
happy, we provide a temporary dummy implementation of
vgic_v3_setup_hw() to allow building for now.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- add Kconfig help text
- use separate Makefile in vgic/ directory
-
can't
easily reuse the existing implementation.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
Changelog v1 ... v2:
- Add Acked-by:
xen/arch/arm/vgic/vgic.c | 44
1 file changed, 44 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic.c
The config register handlers are shared between the v2 and v3 emulation,
so their implementation goes into vgic-mmio.c, to be easily referenced
from the v3 emulation as well later.
This is based on Linux commit 79717e4ac09c, written by Andre Przywara.
Signed-off-by: Andre Przywara
Reviewed-by
When we dump guest state on the Xen console, we also print the state of
IRQs that are on a VCPU.
Add the code to dump the state of an IRQ handled by the new VGIC.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
Changelog v1 ... v2:
- Add Acked-by:
xen/arch/arm/vgic/vgic.c | 25
The ARM arch code requires an interrupt controller emulation to implement
vgic_clear_pending_irqs(), although it is suspected that it is actually
not necessary. Go with a stub for now to make the linker happy.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 8
1 file
The Xen arch code traps system registers writes from the guest and will
relay anything GIC related to the VGIC.
Since this affects only GICv3 (which we don't yet emulate), provide a
stub implementation of vgic_emulate() for now.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
Chan
there is no real technical
reason this struct has to fit in one page, so lifting the limit to two
pages seems like the most pragmatic solution.
Restrict this to compiling with the new VGIC and for ARM64 only.
Signed-off-by: Andre Przywara
---
Changelog v1 ... v2:
- confine change to new VGIC and
As this register is v2 specific, its implementation lives entirely
in vgic-mmio-v2.c.
This register allows setting the source mask of an IPI.
This is based on Linux commit ed40213ef9b0, written by Andre Przywara.
Signed-off-by: Andre Przywara
Reviewed-by: Julien Grall
---
Changelog v1 ... v2
When a VCPU moves to another CPU, we need to adjust the target affinity
of any hardware mapped vIRQs, to observe our "physical-follows-virtual"
policy.
Implement arch_move_irqs() to adjust the physical affinity of all hardware
mapped vIRQs targetting this VCPU.
Signed-off-by: Andr
-by: Andre Przywara
---
Changelog v1 ... v2:
- whitespace fixes
xen/arch/arm/vgic/vgic-v2.c | 66 +
xen/arch/arm/vgic/vgic.h| 1 +
2 files changed, 67 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c
index
Hi,
On 16/03/18 10:48, Jan Beulich wrote:
On 15.03.18 at 21:30, wrote:
>> --- a/xen/common/Makefile
>> +++ b/xen/common/Makefile
>> @@ -19,6 +19,7 @@ obj-y += keyhandler.o
>> obj-$(CONFIG_KEXEC) += kexec.o
>> obj-$(CONFIG_KEXEC) += kimage.o
>> obj-y += lib.o
>> +obj-y += list_sort.o
>
>
Hi,
On 16/03/18 11:32, Jan Beulich wrote:
On 16.03.18 at 12:10, wrote:
>> On 16/03/18 10:48, Jan Beulich wrote:
>> On 15.03.18 at 21:30, wrote:
--- a/xen/common/Makefile
+++ b/xen/common/Makefile
@@ -19,6 +19,7 @@ obj-y += keyhandler.o
obj-$(CONFIG_KEXEC) += kexec.o
Hi,
On 15/03/18 20:30, Andre Przywara wrote:
> When playing around with hardware mapped, level triggered virtual IRQs,
> there is the need to explicitly set the active or pending state of an
> interrupt at some point.
> To prepare the GIC for that, we introduce a set_active_s
Hi,
On 16/03/18 22:52, Stefano Stabellini wrote:
> On Fri, 16 Mar 2018, Julien Grall wrote:
>> On 16/03/2018 21:34, Stefano Stabellini wrote:
>>> On Thu, 15 Mar 2018, Andre Przywara wrote:
>>>> From: Julien Grall
>>>> diff --git a/xen/include/asm-arm/gi
Hi,
On 19/03/18 09:47, Julien Grall wrote:
> Hi Andre,
>
> On 03/15/2018 08:30 PM, Andre Przywara wrote:
>> Triggering an IPI via this register is v2 specific, so the
>> implementation lives entirely in vgic-mmio-v2.c.
>>
>> This is based on Linux commit 55cc01
Hi,
On 19/03/18 14:17, Julien Grall wrote:
> Hi,
>
> On 03/15/2018 08:30 PM, Andre Przywara wrote:
>> Implement the framework for syncing IRQs between our emulation and the
>> list registers, which represent the guest's view of IRQs.
>> This is done in vgic_sync
Hi,
On 06/03/18 18:13, Julien Grall wrote:
> Hi Andre,
>
> On 05/03/18 16:03, Andre Przywara wrote:
>> The new VGIC implementation centers around a struct vgic_irq instance
>> per virtual IRQ.
>> Provide a function to retrieve the right instance for a given IRQ
>&g
Hi,
On 19/03/18 09:30, Julien Grall wrote:
>
>
> On 03/16/2018 04:05 PM, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 15/03/18 20:30, Andre Przywara wrote:
>>> + }
>>> +}
>>> +
>>> +static void gicv2_set_pending_sta
Hi,
On 19/03/18 21:53, Julien Grall wrote:
>
>
> On 03/19/2018 05:32 PM, Andre Przywara wrote:
>> Hi,
>
> Hi,
>
>> On 06/03/18 18:13, Julien Grall wrote:
>>> Hi Andre,
>>>
>>> On 05/03/18 16:03, Andre Przywara wrote:
>>>>
Hi,
On 20/03/18 08:30, Julien Grall wrote:
> Hi,
>
> On 03/15/2018 08:30 PM, Andre Przywara wrote:
>> tl;dr: Coarse changelog below, individual patches have changelogs as
>> well. git branch:
>> http://www.linux-arm.org/git?p=xen-ap.git;a=shortlog;h=refs/heads/vg
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