On 24/11/2023 22:05, Andrew Cooper wrote:
diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index 5cb87f8649..cd4701c5a2 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -1061,13 +1061,26 @@ static const struct hvm_mmio_ops vlapic_mmio_ops = {
.writ
On 27/11/2023 08:40, Jan Beulich wrote:
On 23.11.2023 18:30, Alejandro Vallejo wrote:
@@ -1498,27 +1511,36 @@ static int cf_check lapic_save_regs(struct vcpu *v,
hvm_domain_context_t *h)
*/
static void lapic_load_fixup(struct vlapic *vlapic)
{
-uint32_t id = vlapic->loaded
On 27/11/2023 12:20, Andrew Cooper wrote:
> On 27/11/2023 12:08 pm, Alejandro Vallejo wrote:
>> On 24/11/2023 22:05, Andrew Cooper wrote:
>>>> diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
>>>> index 5cb87f8649..cd4701c5a2 100644
>>>&g
On 27/11/2023 12:24, Jan Beulich wrote:
> On 27.11.2023 13:17, Alejandro Vallejo wrote:
>> On 27/11/2023 08:40, Jan Beulich wrote:
>>> On 23.11.2023 18:30, Alejandro Vallejo wrote:
>>>> @@ -1498,27 +1511,36 @@ static int cf_check lapic_save_regs(struct vcpu
&g
f7b35 ("x86/HVM: fix ID handling of x2APIC emulation")
Signed-off-by: Alejandro Vallejo
Reviewed-by: Roger Pau Monné
Reviewed-by: Andrew Cooper
---
v5:
[Andrew]
* Missing full stop in commit message
* Specifically mention spec violation in the commit message
* Use struct vcpu* dir
On 27/11/2023 13:46, Alejandro Vallejo wrote:
> Both Intel and AMD manuals agree that on x2APIC mode, the APIC LDR and ID
> registers are derivable from each other through a fixed formula.
>
> Xen uses that formula, but applies it to vCPU IDs (which are sequential)
> rather than x2
ement XEN_SYSCTL_get_cpu_policy')
Fixes: 60529dfeca14 ('x86/domctl: Implement XEN_DOMCTL_get_cpu_policy')
Fixes: 14ba07e6f816 ('x86/domctl: Implement XEN_DOMCTL_set_cpumsr_policy')
Signed-off-by: Alejandro Vallejo
---
tools/libs/guest/xg_cpuid_x86.c | 86 +++
no accross free()
Signed-off-by: Alejandro Vallejo
---
tools/libs/guest/xg_cpuid_x86.c | 98 +++--
1 file changed, 45 insertions(+), 53 deletions(-)
diff --git a/tools/libs/guest/xg_cpuid_x86.c b/tools/libs/guest/xg_cpuid_x86.c
index db5aebc815..4453178100 100644
--- a/
that case, the new helper just returns
the legacy mapping.
Signed-off-by: Alejandro Vallejo
---
tools/tests/cpu-policy/test-cpu-policy.c | 128 +++
xen/include/xen/lib/x86/cpu-policy.h | 2 +
xen/lib/x86/policy.c | 75 +++--
3 files changed
IDs are calculated from the CPU policy where the guest topology is
defined. For the time being, the function simply returns the old
relationship, but will eventually return results consistent with the
topology.
Signed-off-by: Alejandro Vallejo
---
xen/arch/x86/cpuid.c | 20
* errno.h => Use xen/errno.h instead
No functional change intended.
Signed-off-by: Alejandro Vallejo
---
xen/lib/x86/cpuid.c | 12 ++--
xen/lib/x86/private.h | 8 +---
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid
This allows toolstack to synthesise sensible topologies for guests. In
particular, this patch causes x2APIC IDs to be packed according to the
topology now exposed to the guests on leaf 0xb.
Signed-off-by: Alejandro Vallejo
---
tools/include/xenguest.h| 15
tools/libs/guest
ts
have topologically consistent information in CPUID
Alejandro Vallejo (6):
xen/x86: Add initial x2APIC ID to the per-vLAPIC save area
tools/xc: Add xc_cpu_policy to the public xenctrl.h header
xen/x86: Refactor xen/lib/x86 so it can be linked in hvmloader
tools/hvmloader: Use c
Move struct xc_cpu_policy data structure out of xg_private.h and into
the public xenguest.h so it can be used by libxl.
Signed-off-by: Alejandro Vallejo
---
tools/include/xenguest.h | 8 +++-
tools/libs/guest/xg_private.h| 10 --
xen/include/xen/lib/x86/cpu
As part of topology correction efforts, APIC IDs can no longer be derived
strictly through the vCPU ID alone. Bring in the machinery for policy
retrieval and parsing in order to generate the proper MADT table and wake
the appropriate CPUs.
Signed-off-by: Alejandro Vallejo
---
tools/firmware
Review-to-self after running in Gitlab:
On 09/01/2024 15:38, Alejandro Vallejo wrote:
> +p->basic.lppp = 0xff;
> +if ( threads_per_pkg < 0xff )
> +p->basic.lppp = threads_per_pkg;
> +
> +switch ( p->x86_vendor )
> +{
> +case X86_VE
This enables a set of follow-up simplifications in the toolstack.
No functional change.
Signed-off-by: Alejandro Vallejo
---
tools/include/xenguest.h | 8 +++-
tools/libs/guest/xg_private.h| 10 --
xen/include/xen/lib/x86/cpu-policy.h | 6 --
3 files
Factor out policy getters/setters from both (CPUID and MSR) policy override
functions. Additionally, use host policy rather than featureset when
preparing the cur policy, saving one hypercall and several lines of
boilerplate.
No functional change intended.
Signed-off-by: Alejandro Vallejo
uired.
Patch 3: Performs the refactor of the policy manipulation code so that it
follows a strict: PULL_POLICIES, MUTATE_POLICY (n times), PUSH_POLICY.
Alejandro Vallejo (3):
tools/xg: Move xc_cpu_policy_t to xenguest.h
tools/xg: Streamline cpu policy serialise/deserialise calls
too
allocating dynamic
memory aside from the policy objects in xen-cpuid. Also minor cleanup
in the policy print call sites.
No functional change intended.
Signed-off-by: Alejandro Vallejo
---
Splitting this patch in several is quite annoying, as it implies
artificially creating duplicates of the
Hi,
On 04/03/2024 07:32, Jan Beulich wrote:
> BARs of size 2Gb and up can't possibly fit below 4Gb: Both the bottom of
> the lower 2Gb range and the top of the higher 2Gb range have special
> purpose. Don't even have them influence whether to (perhaps) relocate
> low RAM.
>
> Reported-by: Neowutra
init() and
early_microcode_init()
(was v7/patch2)
Patch 4 Adds the logic to detect microcode updates being disabled on Intel.
(was v7/patch3)
Alejandro Vallejo (4):
x86/microcode: WARN->INFO for the "no ucode loading" log message
x86/microcode: Ignore microcode loading interface
Some hypervisors report ~0 as the microcode revision to mean "don't issue
microcode updates". Ignore the microcode loading interface in that case.
Signed-off-by: Alejandro Vallejo
Reviewed-by: Jan Beulich
---
v8:
* Added missing newline in printk statement
* Reduced indent
Move MSR_ARCH_CAPS read code from tsx_init() to early_cpu_init(). Because
microcode updates might make them that MSR to appear/have different values
we also must reload it after a microcode update in early_microcode_init().
Signed-off-by: Alejandro Vallejo
Reviewed-by: Jan Beulich
---
v8:
* No
Currently there's a printk statement triggered when no ucode loading
facilities are discovered. This statement should have severity INFO rather
than WARNING because it's not reporting anything wrong. Warnings ought
to be reserved for recoverable system errors.
Signed-off-by: Alejand
g
set then simply disable the "apply_microcode" handler so we can't even try
to perform update (as it's known to be silently dropped).
While at it, remove the Intel family check, as microcode loading is
supported on every Intel64 CPU.
Signed-off-by: Alejandro Vallejo
Reviewe
Hi,
On Mon, Sep 04, 2023 at 08:51:31AM +0200, Jan Beulich wrote:
> On 02.09.2023 18:21, Javi Merino wrote:
> > Closes #154
> >
> > Signed-off-by: Javi Merino
>
> The title isn't really in line with ...
>
> > --- a/tools/misc/xencov_split
> > +++ b/tools/misc/xencov_split
> > @@ -1,5 +1,7 @@
>
d-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
---
tools/include/xenctrl.h | 16
tools/libs/ctrl/xc_domain.c | 22 ++
2 files changed, 38 insertions(+)
diff --git a/tools/include/xenctrl.h b/tools/in
and ensure the returned domid matches the requested one. The domtctl
will find the domid faster too, because that uses hashed lists.
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
---
tools/libs/light/libxl_dom.c | 15
It has 2 avoidable occurences
* Check whether a domain is valid, which can be done faster with
xc_domain_getinfo_single()
* Domain discovery, which can be done much faster with the sysctl
interface through xc_domain_getinfolist().
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
migrate the callers interested in more than 1 domain to the the *list()
version.
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
---
tools/include/xenctrl.h | 5 +
tools/python/xen/lowlevel/xc/xc.c | 29
so we can (hopefully) get away with a
single hypercall in a typical system.
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Juergen Gross
---
tools/helpers/init-xenstore-domain.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/tools/helpers/ini
en-project/xen#105
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Jan Beulich
Cc: Julien Grall
Cc: Stefano Stabellini
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
---
tools/include/xenctrl.h | 43 ---
tools/libs/ctrl/xc_dom
l itself.
Alejandro Vallejo (7):
tools: Make some callers of xc_domain_getinfo use
xc_domain_getinfolist
tools: Create xc_domain_getinfo_single()
tools: Refactor the console/io.c to avoid using xc_domain_getinfo()
tools: Make init-xenstore-domain use xc_domain_getinfolist()
tools: Modif
Move calls that require a information about a single precisely identified
domain to the new xc_domain_getinfo_single().
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Tim Deegan
Cc: George Dunlap
Cc: Juergen Gross
---
tools/console/client/main.c
Ah, I didn't notice that header. Sure, added locally on v2.
Cheers,
Alejandro
On Wed, Apr 26, 2023 at 05:20:01PM +0200, Juergen Gross wrote:
> Please include instead of defining ARRAY_SIZE().
>
> With that changed:
>
> Reviewed-by: Juergen Gross
>
>
> Juergen
Answers inlined
On Thu, Apr 27, 2023 at 10:51:03AM +0100, Andrew Cooper wrote:
> Just as a note for the subject, we more commonly write function names
> with ()'s.
No harm in abiding by that. Done on v2.
> > +"crashed", (info[i].flags & XEN_DOMINF_shutdown) &&
> > +
On Thu, Apr 27, 2023 at 01:35:18PM +0100, Andrew Cooper wrote:
>
> > +xc_domaininfo_t di;
> > unsigned int nr_leaves, nr_msrs;
> > uint32_t err_leaf = -1, err_subleaf = -1, err_msr = -1;
> > /*
> > @@ -291,13 +292,13 @@ static int xc_cpuid_xend_policy(
> > xen_cpuid_leaf_t
migrate the callers interested in more than 1 domain to the the *list()
version.
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
---
tools/include/xenctrl.h | 12
tools/python/xen/lowlevel/xc/xc.c | 28
d-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
---
tools/include/xenctrl.h | 16
tools/libs/ctrl/xc_domain.c | 23 +++
2 files changed, 39 insertions(+)
diff --git a/tools/include/xenctrl.h b/tools/in
simplified to
only use its fastpath.
With the DOMCTL amended, the new xc_domain_getinfo_single() drops its
stricter check, becoming a simple wrapper to invoke the hypercall itself.
Alejandro Vallejo (7):
tools: Make some callers of xc_domain_getinfo() use
xc_domain_getinfolist
so we can (hopefully) get away with a
single hypercall in a typical system.
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Juergen Gross
---
tools/helpers/init-xenstore-domain.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/tools/helpers/ini
and ensure the returned domid matches the requested one. The domtctl
will find the domid faster too, because that uses hashed lists.
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
---
tools/libs/light/libxl_dom.c | 15
It has 2 avoidable occurences
* Check whether a domain is valid, which can be done faster with
xc_domain_getinfo_single()
* Domain discovery, which can be done much faster with the sysctl
interface through xc_domain_getinfolist().
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Move calls that require a information about a single precisely identified
domain to the new xc_domain_getinfo_single().
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Tim Deegan
Cc: George Dunlap
Cc: Juergen Gross
---
tools/console/client/main.c
en-project/xen#105
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Jan Beulich
Cc: Julien Grall
Cc: Stefano Stabellini
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
---
tools/include/xenctrl.h| 43
tools/libs/ctrl/xc_domain
Sounds good to me.
Cheers,
Alejandro
On Fri, Apr 28, 2023 at 01:40:50PM +0100, Andrew Cooper wrote:
> I'm recommend having a comment here, saying something like /* Commonly
> dom0 is the only domain, but buffer a little for efficiency. */
>
> Because this is also the justification for why we don
On Fri, Apr 28, 2023 at 01:33:45PM +0100, Andrew Cooper wrote:
> On 28/04/2023 11:41 am, Alejandro Vallejo wrote:
> > It has 2 avoidable occurences
> >
> > * Check whether a domain is valid, which can be done faster with
> > xc_domain_getinfo_single()
> > * Do
On Tue, May 02, 2023 at 08:53:31AM +0200, Jan Beulich wrote:
> I'm also having a hard time seeing what failure case the test ended
> up encountering: There are only two errors which can occur - one
> from the XSM hook (which is mishandled, and I'll make a separate
> patch for that) and the other fr
e DOMCTL ammended, the new xc_domain_getinfo_single() drops its
stricter check, becoming a simple wrapper to invoke the hypercall itself.
Alejandro Vallejo (3):
tools: Modify single-domid callers of xc_domain_getinfolist()
tools: Use new xc function for some xc_domain_getinfo() calls
domctl
and ensure the returned domid matches the requested one. The domtctl
will find the domid faster too, because that uses hashed lists.
Signed-off-by: Alejandro Vallejo
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
Cc: Christian Lindig
v3:
* Replaced single-domid
en-project/xen#105
Signed-off-by: Alejandro Vallejo
Reviewed-by: Andrew Cooper
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Jan Beulich
Cc: Julien Grall
Cc: Stefano Stabellini
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
v3:
* No changes
---
tools/include/xenctrl.
Move calls that require a information about a single precisely identified
domain to the new xc_domain_getinfo_single().
Signed-off-by: Alejandro Vallejo
Reviewed-by: Andrew Cooper
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Tim Deegan
Cc: George Dunlap
Cc: Juergen Gross
v3
On Tue, May 02, 2023 at 12:13:36PM +0100, Alejandro Vallejo wrote:
> xc_domain_getinfolist() internally relies on a sysctl that performs
> a linear search for the domids. Many callers of xc_domain_getinfolist()
> who require information about a precise domid are much better of
On Tue, May 02, 2023 at 12:13:37PM +0100, Alejandro Vallejo wrote:
> Move calls that require a information about a single precisely identified
> domain to the new xc_domain_getinfo_single().
>
> Signed-off-by: Alejandro Vallejo
> Reviewed-by: Andrew Cooper
>
> ---
>
AMD reports support for CpuidUserDis in CPUID and provides the toggle in HWCR.
This patch adds the positions of both of those bits to both xen and tools.
No functional change.
Signed-off-by: Alejandro Vallejo
---
tools/libs/light/libxl_cpuid.c | 1 +
tools/misc/xen-cpuid.c
bing path and
the context switching path.
Patch 3 enables HVM guests to use CpuidUserDis as if it was CPUID faulting,
saving an avoidable roundtrip through the hypervisor at fault handling.
Alejandro Vallejo (3):
x86: Add AMD's CpuidUserDis bit definitions
x86: Add support for CpuidUserDis
Includes a refactor to move vendor-specific probes to vendor-specific
files. Furthermore, because CpuIdUserDis is reported in Cpuid itself,
the extended leaf containing that bit must be retrieved before calling
c_early_init()
Signed-off-by: Alejandro Vallejo
---
xen/arch/x86/cpu/amd.c
This is in order to aid guests of AMD hardware that we have exposed
CPUID faulting to. If they try to modify the Intel MSR that enables
the feature, trigger levelling so AMD's version of it (CpuidUserDis)
is used instead.
Signed-off-by: Alejandro Vallejo
---
xen/arch/x86/msr.c | 9 +++
On Tue, May 09, 2023 at 04:41:49PM +0200, Jan Beulich wrote:
> > I asked Alejandro to do it like this.
> >
> > Advertising this to guests requires plumbing another MSR into the
> > infrastructure which isn't quite set up properly let, and is in flux
> > from my work.
> >
> > For now, this just le
ified to
only use its fastpath.
With the DOMCTL ammended, the new xc_domain_getinfo_single() drops its
stricter check, becoming a simple wrapper to invoke the hypercall itself.
Alejandro Vallejo (3):
tools: Modify single-domid callers of xc_domain_getinfolist()
tools: Use new xc function
and ensure the returned domid matches the requested one. The domtctl
will find the domid faster too, because that uses hashed lists.
Signed-off-by: Alejandro Vallejo
Reviewed-by: Andrew Cooper
Acked-by: Christian Lindig
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
Cc
en-project/xen#105
Signed-off-by: Alejandro Vallejo
Reviewed-by: Andrew Cooper
Acked-by: Anthony PERARD
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Jan Beulich
Cc: Julien Grall
Cc: Stefano Stabellini
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Juergen Gross
---
tools/include/xenctrl.
Move calls that require a information about a single precisely identified
domain to the new xc_domain_getinfo_single().
Signed-off-by: Alejandro Vallejo
Reviewed-by: Andrew Cooper
---
Cc: Andrew Cooper
Cc: Wei Liu
Cc: Anthony PERARD
Cc: Tim Deegan
Cc: George Dunlap
Cc: Juergen Gross
v4
y adds definitions to various places in CPUID and MSR
Patch 2 moves vendor-specific code on probe_cpuid_faulting() to amd.c/intel.c
Patch 3 adds support for CpuidUserDis, hooking it in the probing path and
the context switching path.
Alejandro Vallejo (3):
x86: Add AMD's CpuidUserDi
Move vendor-specific checks to the vendor-specific callers.
No functional change.
Signed-off-by: Alejandro Vallejo
---
v2:
* Patch factored out from patch2 of v1
---
xen/arch/x86/cpu/amd.c| 10 +-
xen/arch/x86/cpu/common.c | 11 ---
xen/arch/x86/cpu/intel.c | 9
AMD reports support for CpuidUserDis in CPUID and provides the toggle in HWCR.
This patch adds the positions of both of those bits to both xen and tools.
No functional change.
Signed-off-by: Alejandro Vallejo
---
tools/libs/light/libxl_cpuid.c | 1 +
tools/misc/xen-cpuid.c
Because CpuIdUserDis is reported in CPUID itself, the extended leaf
containing that bit must be retrieved before calling c_early_init()
Signed-off-by: Alejandro Vallejo
---
v2:
* Style fixes
* MSR index inlined in rdmsr/wrmsr
* Swapped Intel's conditional guard so typically true cond
On Wed, May 10, 2023 at 10:15:31AM +0200, Jan Beulich wrote:
> On 09.05.2023 12:05, Andrew Cooper wrote:
> > On 08/05/2023 2:18 pm, Jan Beulich wrote:
> >> On 05.05.2023 19:57, Alejandro Vallejo wrote:
> >>> This is in order to aid guests of AMD hardware that we hav
On Mon, May 08, 2023 at 11:06:31AM +0200, Jan Beulich wrote:
> On 05.05.2023 19:57, Alejandro Vallejo wrote:
> > Nowadays AMD supports trapping the CPUID instruction from ring3 to ring0,
>
> Since it's relevant for PV32: Their doc talks about CPL > 0, i.e. not just
>
On Thu, May 11, 2023 at 11:41:13AM +0200, Jan Beulich wrote:
> On 09.05.2023 18:43, Alejandro Vallejo wrote:
> > --- a/xen/include/public/arch-x86/cpufeatureset.h
> > +++ b/xen/include/public/arch-x86/cpufeatureset.h
> > @@ -287,6 +287,7 @@ XEN_CPUFEATURE(AVX_IFMA, 10
On Thu, May 11, 2023 at 01:05:42PM +0200, Jan Beulich wrote:
> > --- a/xen/arch/x86/cpu/amd.c
> > +++ b/xen/arch/x86/cpu/amd.c
> > @@ -279,8 +279,12 @@ static void __init noinline amd_init_levelling(void)
> > * that can only be present when Xen is itself virtualized (because
> > * it can
Move vendor-specific checks to the vendor-specific callers. While at it
move the synth cap setters to the callers too, as it's needed for a later
patch and it's not a functional change either.
No functional change.
Signed-off-by: Alejandro Vallejo
Reviewed-by: Jan Beulich
---
v3:
*
Because CpuIdUserDis is reported in CPUID itself, the extended leaf
containing that bit must be retrieved before calling c_early_init()
Signed-off-by: Alejandro Vallejo
---
v3:
* Moved LCAP_* setters to the callers in patch1/v3
* Added rationale for checking CPUID faulting before CpuidUserDis
el.c
Patch 2 adds support for CpuidUserDis, hooking it in the probing path and
the context switching path.
Alejandro Vallejo (2):
x86: Refactor conditional guard in probe_cpuid_faulting()
x86: Add support for CpuidUserDis
xen/arch/x86/cpu/amd.c | 32 -
xen/arch/x86/cpu/
This is AMD's version of Intel's Enhanced IBRS. Exposed in CPUID
and toggled in EFER.
Signed-off-by: Alejandro Vallejo
---
tools/libs/light/libxl_cpuid.c | 1 +
tools/misc/xen-cpuid.c | 2 ++
xen/arch/x86/include/asm/cpufeature.h | 1 +
xe
dom0 is set up, just like setting
SPEC_CTRL.
Signed-off-by: Alejandro Vallejo
---
xen/arch/x86/setup.c | 3 +++
xen/arch/x86/smpboot.c | 3 +++
xen/arch/x86/spec_ctrl.c | 52
3 files changed, 43 insertions(+), 15 deletions(-)
diff --git a/xen/arch
Expose AutoIBRS to HVM guests, because they can just use it. Make sure
writes to EFER:AIBRSE are gated on the feature being exposed. Also hide
EFER:AIBRSE from PV guests as they have no say in the matter.
Signed-off-by: Alejandro Vallejo
---
xen/arch/x86/hvm/hvm.c | 3
h 3 exposes the feature to HVM guests.
Alejandro Vallejo (3):
x86: Add bit definitions for Automatic IBRS
x86: Add support for AMD's Automatic IBRS
x86: Expose Automatic IBRS to guests
tools/libs/light/libxl_cpuid.c | 1 +
tools/misc/xen-cpuid.c | 2
On Fri, May 26, 2023 at 12:28:39PM -0400, Jason Andryuk wrote:
> > if ( boot_cpu_data.extended_cpuid_level >= 0x8008 )
> > +{
> > cpuid(0x8008, &tmp, &e8b, &tmp, &tmp);
> > +cpuid(0x8021, &e21a, &tmp, &tmp, &tmp);
> > +}
>
> Do you need to check boot_cpu_d
On Fri, May 26, 2023 at 05:46:51PM +0100, Andrew Cooper wrote:
> AIBRS and EIBRS are very much not the same, and I argued hard to not
> have Linux confuse the too, but alas.
>
> Don't mention EIBRS at all.
>
> Simply "Auto IBRS is a new feature in AMD Zen4 CPUs and late, intended
> to reduce the
On Tue, May 30, 2023 at 10:25:36AM +0200, Jan Beulich wrote:
> On 26.05.2023 17:00, Alejandro Vallejo wrote:
> > --- a/xen/arch/x86/smpboot.c
> > +++ b/xen/arch/x86/smpboot.c
> > @@ -376,6 +376,9 @@ void start_secondary(void *unused)
> > {
> &
On Fri, May 26, 2023 at 04:00:43PM +0100, Alejandro Vallejo wrote:
> diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
> index 74e3915a4d..09cfef2676 100644
> --- a/xen/arch/x86/setup.c
> +++ b/xen/arch/x86/setup.c
> @@ -2036,6 +2036,9 @@ void __init noreturn __start_xen(unsi
Expose AutoIBRS to HVM guests. EFER is swapped by VMRUN, so Xen only has to
make sure writes to EFER.AIBRSE are gated on the feature being exposed.
Also hide EFER.AIBRSE from PV guests as they have no say in the matter.
Signed-off-by: Alejandro Vallejo
Reviewed-by: Andrew Cooper
---
v2
D and EFER.
Patch 2 exposes the feature to HVM guests.
Patch 3 Hooks up AutoIBRS to spec_ctrl. so it's used when IBRS is picked.
It also tweaks the heuristics so AutoIBRS is preferred over
retpolines as BTI mitigation. This is enough to protect Xen.
Alejandro Vallejo (3):
This is an AMD feature to reduce the IBRS handling overhead. Once enabled,
processes running at CPL=0 are automatically IBRS-protected even if
SPEC_CTRL.IBRS is not set. Furthermore, the RAS/RSB is cleared on VMEXIT.
The feature is exposed in CPUID and toggled in EFER.
Signed-off-by: Alejandro
In cases where AutoIBRS is supported by the host:
* Prefer AutoIBRS to retpolines as BTI mitigation in heuristics
calculations.
* Always enable AutoIBRS if IBRS is chosen as a BTI mitigation.
* Avoid stuffing the RAS/RSB on VMEXIT if AutoIBRS is enabled.
Signed-off-by: Alejandro Vallejo
300Mhz CPU (Pentium 2 era) from 1998 when MMX was the headline
> feature, sporting 64M of RAM. Being a 32-bit processor, it hasn't been able
> to run Xen for about a decade now, so drop the quirk entirely.
>
> Signed-off-by: Andrew Cooper
> ---
> CC: Jan Beulich
> CC:
Moves sti directly after the cr2 read and immediately after the #PF
handler.
While in the area, remove redundant q suffix to a movq in entry.S
Signed-off-by: Alejandro Vallejo
---
I don't think this is a bug as much as an accident about to happen. Even if
there's no cases at the momen
On Thu Sep 12, 2024 at 10:49 AM BST, Andrew Cooper wrote:
> On 11/09/2024 3:58 pm, Alejandro Vallejo wrote:
> > diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
> > index b8482de8ee..ef803f6288 100644
> > --- a/xen/arch/x86/x86_64/entry.S
> > +++ b/
Monné
> CC: Daniel P. Smith
> CC: Frediano Ziglio
> CC: Alejandro Vallejo
>
> v2:
> * Rebase over the introduction of trampoline_perm_end
> * Fix the description of the boot stack position
> ---
> xen/arch/x86/include/asm/trampoline.h | 57 +
On Tue Nov 26, 2024 at 9:40 AM GMT, Jan Beulich wrote:
> On 25.11.2024 19:51, Alejandro Vallejo wrote:
> > On Mon Nov 25, 2024 at 12:05 PM GMT, Jan Beulich wrote:
> >> On 15.11.2024 12:51, Alejandro Vallejo wrote:
> >>> Describe sysctl/readconsole as a TOML specif
Hi,
I've been trying to run this series for a while, but it crashes very
frequentyly starting from the patch that generalizes the mapcache. I think I've
tracked it down to this patch.
On Mon Nov 11, 2024 at 1:11 PM GMT, Elias El Yandouzi wrote:
> From: Hongyan Xia
>
> Building a PV dom0 is alloc
On Thu Jan 30, 2025 at 9:17 AM GMT, Jan Beulich wrote:
> On 29.01.2025 17:25, Roger Pau Monné wrote:
> > On Tue, Jan 28, 2025 at 06:42:38PM +, Alejandro Vallejo wrote:
> >> On Tue Jan 28, 2025 at 5:45 PM GMT, Roger Pau Monné wrote:
> >>> On Tue, Jan 28, 2025
er and the toolstack currently engage in a shared
assumption that for every vCPU apicid == 2 * vcpuid. This series removes such
assumption from hvmloader, by making it read the APIC ID of each vCPU and
storing it for later use.
Alejandro Vallejo (2):
tools/hvmloader: Retrieve APIC IDs from t
used for the vcpu id.
Signed-off-by: Alejandro Vallejo
---
v1->v2:
* Removed "(x2)" from the comment of cpu_to_apicid.
* Added "APIC ID" to the printed string on AP boot up.
Changes from the v7 version of this patch in the longer topology series:
* s/cpu_to
using it uninitialised. Note that bringing
up the APs doesn't need the APIC in hvmloader becasue it always runs
virtualized and uses the PV interface.
Signed-off-by: Alejandro Vallejo
---
v1->v2:
* No changes
Changes wrt original series
* No changes (it was wrongly stated in v1 that s
On Tue Feb 4, 2025 at 3:07 PM GMT, Jan Beulich wrote:
> On 04.02.2025 15:45, Alejandro Vallejo wrote:
> > --- a/tools/firmware/hvmloader/config.h
> > +++ b/tools/firmware/hvmloader/config.h
> > @@ -48,8 +48,9 @@ extern uint8_t ioapic_version;
> >
> >
On Wed Feb 5, 2025 at 12:44 AM GMT, Stefano Stabellini wrote:
> Hi all,
>
> I would like to propose to enable the UBSAN config option in our Gitlab
> pipelines. The attached patch (just for testing, do not commit) enables
> UBSAN on the Xen build jobs used for most of the ARM and x86 tests. The
> p
On Tue Feb 4, 2025 at 3:46 PM GMT, Jan Beulich wrote:
> On 04.02.2025 16:25, Alejandro Vallejo wrote:
> > On Tue Feb 4, 2025 at 3:07 PM GMT, Jan Beulich wrote:
> >> On 04.02.2025 15:45, Alejandro Vallejo wrote:
> >>> --- a/tools/firmware/hvmloader/config.h
> &
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