On 27/11/2024 10:03 am, Javi Merino wrote:
> On Tue, Nov 26, 2024 at 08:58:59PM +, Andrew Cooper wrote:
>> The SDM instructs software to write 0 to ESR prior to reading it. However,
>> due to an original Pentium erratum, most logic skips the write based on there
>> being more than 3 LVTs; a st
On 11/26/24 18:21, Denis Mukhin via B4 Relay wrote:
From: Denis Mukhin
While working on console forwarding for virtual NS8250 I stepped into
flask_domain_alloc_security()
where break statement was missing in default case which violates MISRA
rule 16.4.
Fixed everywhere in hooks.c.
Signed-o
Move the direct message handling function in its own source file and
rename it to have a ffa_ prefix.
This is a preparation to add support for indirect messages which will
go into this newly created source file.
Signed-off-by: Bertrand Marquis
Reviewed-by: Jens Wiklander
---
Changes in v3:
- add
On 27/11/2024 14:24, Carlo Nonato wrote:
>
>
> Hi Michal,
>
> On Wed, Nov 27, 2024 at 11:48 AM Michal Orzel wrote:
>> On 19/11/2024 15:13, Carlo Nonato wrote:
>>>
>>>
>>> Last Level Cache (LLC) coloring allows to partition the cache in smaller
>>> chunks called cache colors.
>>>
>>> Since no
On 19/11/2024 15:13, Carlo Nonato wrote:
>
>
> LLC coloring needs to know the last level cache layout in order to make the
> best use of it. This can be probed by inspecting the CLIDR_EL1 register,
> so the Last Level is defined as the last level visible by this register.
> Note that this excl
From: Penny Zheng
In Xen, SMMU subsystem is supported for MMU system only. The reason being SMMU
driver uses the same page tables as MMU.
Thus, we make it dependent on CONFIG_MMU.
Signed-off-by: Penny Zheng
Signed-off-by: Ayan Kumar Halder
---
Changes from
v1 - 1. HAS_PASSTHROUGH is now encl
CONFIG_EARLY_UART_SIZE is introduced to let user provide physical size of
early UART. Unlike MMU where we map a page in the virtual address space,
here we need to know the exact physical size to be mapped.
As VA == PA in case of MPU, the memory layout follows exactly the hardware
configuration. As
This patch serie concludes earlyboot support for Arm-v8R AArch64 MPU systems.
Depends on "[PATCH v6 0/3] Enable early bootup of AArch64 MPU systems".
Ayan Kumar Halder (1):
xen/mpu: Map early uart when earlyprintk on
Penny Zheng (1):
xen/mmu: enable SMMU subsystem only in MMU
xen/arch/arm/
Make use and required to have bit 15 convention respected by secure
world (having bit 15 of IDs set for secure endpoints and non-set for
non-secure ones).
If any secure partition has an ID with bit 15 not set, it will not be
possible to contact or detect them.
Print an error log during probe for ea
Rework firmware discovery during probe:
- move prints into the probe
- rename ffa_version to ffa_fw_version as the variable identifies the
version of the firmware and not the one we support
- add error prints when allocation fail during probe
No functional changes.
Signed-off-by: Bertrand Marqu
Store the list of ABI we need in a list and go through the list instead
of having a list of conditions inside the code.
No functional change.
Signed-off-by: Bertrand Marquis
---
Changes in v3:
- remove const attribute for id in ffa_fw_abi struct
Changes in v2:
- Store a string version of ABI nee
This serie contains various patches to rework how firmware discovery and
feature detection is done and allow to have a more fine granular
filtering of the calls we do or not to the firmware.
There is also a patch introducing the use of the "bit 15" convention
from the FF-A specification to disting
On 27/11/2024 7:15 am, Jan Beulich wrote:
> The reg-reg forms should cause #UD; they come into existence only with
> APX, where MOVBE also extends BSWAP (for the latter not being "eligible"
> to a REX2 prefix).
>
> Signed-off-by: Jan Beulich
Reviewed-by: Andrew Cooper
Create a bitmap to store which feature is supported or not by the
firmware and use it to filter which calls are done to the firmware.
While there reoder ABI definition by numbers to easily find the min and
max ones.
Signed-off-by: Bertrand Marquis
Reviewed-by: Jens Wiklander
---
Changes in v3:
Fix FFA version negotiation with the firmware to follow the
specification guidance more closely (see FF-A Specification Version 1.1
in chapter 13.2.1).
When the firmware returns OK we can have several cases:
- the version requested is accepted but the firmware supports a greater
one in the same m
When an RXTX buffer is mapped by a VM transmit it to the SPMC when it
supports RX_ACQUIRE.
As a consequence of that, we must acquire the RX buffer of a VM from the
SPMC when we want to use it:
- create a generic acquire and release function to get the rx buffer of
a VM which gets it from the SPMC
Rework the partition info get implementation to use the correct size of
structure depending on the version of the protocol and simplifies the
structure copy to use only memcpy and prevent recreating the structure
each time.
The goal here is to have an implementation that will be easier to
maintain
Add support for FFA_MSG_SEND2 to send indirect messages from a VM to a
secure partition.
Signed-off-by: Bertrand Marquis
---
Changes in v3:
- in ffa_handle_msg_send2 use ffa_get_vm_id instead of a local variable
to make sure that we use the right VM ID as source without having a
potential sol
Remove the per VM flag to store if notifications are enabled or not as
the only case where they are not, if notifications are enabled globally,
will make the VM creation fail.
Also use the opportunity to always give the notifications interrupts IDs
to VM. If the firmware does not support notificati
On 27/11/2024 8:20 am, Jan Beulich wrote:
> On 26.11.2024 21:58, Andrew Cooper wrote:
>> @@ -1389,8 +1381,7 @@ static void cf_check error_interrupt(void)
>> unsigned int i;
>>
>> /* First tickle the hardware, only then report what went on. -- REW */
>> -apic_write(APIC_ESR, 0);
>> -
On 27/11/2024 8:38 am, Roger Pau Monné wrote:
> On Tue, Nov 26, 2024 at 08:58:59PM +, Andrew Cooper wrote:
>> The SDM instructs software to write 0 to ESR prior to reading it. However,
>> due to an original Pentium erratum, most logic skips the write based on there
>> being more than 3 LVTs; a
Found because of yesterday's Pentium errata fun, and trying to
complete/publish the XSA-462 PoC.
Andrew Cooper (2):
x86/vlapic: Fix handling of writes to APIC_ESR
x86/vlapic: Drop vlapic->esr_lock
xen/arch/x86/hvm/vlapic.c | 27 +++---
xen/arch/x86/include/as
Xen currently presents APIC_ESR to guests as a simple read/write register.
This is incorrect. The SDM states:
The ESR is a write/read register. Before attempt to read from the ESR,
software should first write to it. (The value written does not affect the
values read subsequently; only zero
With vlapic->hw.pending_esr held outside of the main regs page, it's much
easier to use atomic operations.
Use xchg() in vlapic_reg_write(), and *set_bit() in vlapic_error().
The only interesting change is that vlapic_error() now needs to take an
err_bit rather than an errmask, but thats fine for
On 26.11.2024 21:58, Andrew Cooper wrote:
> @@ -1389,8 +1381,7 @@ static void cf_check error_interrupt(void)
> unsigned int i;
>
> /* First tickle the hardware, only then report what went on. -- REW */
> -apic_write(APIC_ESR, 0);
> -v = apic_read(APIC_ESR);
> +v = apic_read_
On Tue, Nov 26, 2024 at 05:06:15PM +, Javi Merino wrote:
> The logic to read the APIC_ESR was copied from linux in a commit from
> 2002: 4676bbf96dc8 (bitkeeper revision
> 1.2 (3ddb79c9KusG02eh7i-uXkgY0IksKA), 2002-11-20). In linux 3.14,
> this logic was fixed to follow the Intel SDM (see comm
On 26.11.2024 15:27, Andrew Cooper wrote:
> On 25/11/2024 2:27 pm, Jan Beulich wrote:
>> Before we start actually adjusting behavior when ERMS is available,
>> follow Linux commit 161ec53c702c ("x86, mem, intel: Initialize Enhanced
>> REP MOVSB/STOSB") and zap the CPUID-derived feature flag when th
On 26.11.2024 18:13, Andrew Cooper wrote:
> On 25/11/2024 2:28 pm, Jan Beulich wrote:
>> ---
>> We may want to consider branching over the REP STOSQ as well, if the
>> number of qwords turns out to be zero.
>
> Until FSR{S,M} (Fast Short Rep {STO,MOV}SB), which is far newer than
> ERMS, passing 0
On 15.11.2024 14:12, Daniel P. Smith wrote:
> Add a domid field to struct boot_domain to hold the assigned domain id for the
> domain. During initialization, ensure all instances of struct boot_domain have
> the invalid domid to ensure that the domid must be set either by convention or
> configurat
On 19/11/2024 15:13, Carlo Nonato wrote:
>
>
> Last Level Cache (LLC) coloring allows to partition the cache in smaller
> chunks called cache colors.
>
> Since not all architectures can actually implement it, add a HAS_LLC_COLORING
> Kconfig option.
> LLC_COLORS_ORDER Kconfig option has a ran
On Tue, Nov 26, 2024 at 08:58:59PM +, Andrew Cooper wrote:
> The SDM instructs software to write 0 to ESR prior to reading it. However,
> due to an original Pentium erratum, most logic skips the write based on there
> being more than 3 LVTs; a stand-in to identify the Pentium.
>
> Xen, being
On 26.11.2024 20:16, Andrew Cooper wrote:
> On 25/11/2024 2:28 pm, Jan Beulich wrote:
>> Move the function to its own assembly file. Having it in C just for the
>> entire body to be an asm() isn't really helpful. Then have two flavors:
>> A "basic" version using qword steps for the bulk of the oper
On Tue, Nov 26, 2024 at 08:58:59PM +, Andrew Cooper wrote:
> The SDM instructs software to write 0 to ESR prior to reading it. However,
> due to an original Pentium erratum, most logic skips the write based on there
> being more than 3 LVTs; a stand-in to identify the Pentium.
>
> Xen, being
On 26.11.2024 21:07, Andrew Cooper wrote:
> On 26/11/2024 5:06 pm, Javi Merino wrote:
>> The logic to read the APIC_ESR was copied from linux in a commit from
>> 2002: 4676bbf96dc8 (bitkeeper revision
>> 1.2 (3ddb79c9KusG02eh7i-uXkgY0IksKA), 2002-11-20). In linux 3.14,
>> this logic was fixed to f
On 2024/11/26 17:47, Jan Beulich wrote:
> On 26.11.2024 07:02, Chen, Jiqian wrote:
>> On 2024/11/25 20:47, Roger Pau Monné wrote:
>>> On Mon, Nov 25, 2024 at 03:44:52AM +, Chen, Jiqian wrote:
On 2024/11/21 17:52, Roger Pau Monné wrote:
> On Thu, Nov 21, 2024 at 03:05:14AM +, Chen,
On 26.11.2024 20:58, Andrew Cooper wrote:
> On 25/11/2024 2:29 pm, Jan Beulich wrote:
>> Stop the compiler from inlining non-trivial memset() and memcpy() (for
>> memset() see e.g. map_vcpu_info() or kimage_load_segments() for
>> examples). This way we even keep the compiler from using REP STOSQ /
On 15.11.2024 14:12, Daniel P. Smith wrote:
> --- /dev/null
> +++ b/xen/arch/x86/include/asm/bootdomain.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Copyright (c) 2024 Apertus Solutions, LLC
> + * Author: Daniel P. Smith
> + * Copyright (c) 2024 Christopher C
From: Julien Grall
All the code in arch/arm32/lib/ where copied from Linux 3.16
and never re-synced since then.
A few years ago, Linux got rid of __memzero() because the implementation
is very similar to memset(p,0,n) and the current use of __memzero()
interferes with optimization. See full comm
Hi,
On 26/11/2024 08:41, Jan Beulich wrote:
On 25.11.2024 21:15, Julien Grall wrote:
Hi Jan,
Sorry for the late answer.
On 01/10/2024 16:16, Jan Beulich wrote:
No functional change, albeit all globals now become hidden, and aliasing
symbols (__aeabi_{u,}idiv) as well as __memzero lose their
On 27/11/2024 11:55, Julien Grall wrote:
>
>
> From: Julien Grall
>
> All the code in arch/arm32/lib/ where copied from Linux 3.16
> and never re-synced since then.
>
> A few years ago, Linux got rid of __memzero() because the implementation
> is very similar to memset(p,0,n) and the curren
Signed-off-by: Oleksii Kurochko
---
xen/arch/riscv/include/asm/page.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/riscv/include/asm/page.h
b/xen/arch/riscv/include/asm/page.h
index 91b1194b55..bf3f75e85d 100644
--- a/xen/arch/riscv/include/asm/page.h
+++ b/xen/ar
The current patch series introduces the relocation of the host device tree file
to free up low memory and also it is expected that discard_initial_modules()
will be called sooner or later, it will discard the FDT boot module,
and remove_early_mappings() will destroy the early mappings.
In addition
relocate_fdt() relocates FDT to Xen heap instead of using early mapping
as it is expected that discard_initial_modules() ( is supposed to call
in the future ) discards the FDT boot module and remove_early_mappings()
destroys the early mapping.
To implement that the following things are introduced
Introduce set_fixmap() and clear_fixmap() functions to manage mappings
in the fixmap region. The set_fixmap() function maps a 4k page ( as only L0
is expected to be updated; look at setup_fixmap_mappings() ) at a specified
fixmap entry using map_pages_to_xen(), while clear_fixmap() removes the
mapp
Introduce the destroy_xen_mappings() function, which removes page
mappings in Xen's page tables between a start address s and an end
address e.
The function ensures that both s and e are page-aligned
and verifies that the start address is less than or equal to the end
address before calling pt_upda
KConfig HAS_CMO is introduced to handle if the platform has CMO related
extenstions ( such as Zicbom, Zicboz, Zicbop etc ) or not.
if HAS_CMO isn't set stubs for clean_and_invalidate_dcache_va_range()
and clean_dcache_va_range() are implemented as just returning
-EOPNOTSUPP.
Our current platform
Relocate FDT to Xen heap instead of using early mapping as it is
expected that discard_initial_modules() ( is supposed to call in
the future ) discards the FDT boot module and remove_early_mappings()
destroys the early mapping.
Unflatten a device tree, creating the tree of struct device_node.
It a
On 27.11.2024 11:55, Julien Grall wrote:
> From: Julien Grall
>
> All the code in arch/arm32/lib/ where copied from Linux 3.16
> and never re-synced since then.
>
> A few years ago, Linux got rid of __memzero() because the implementation
> is very similar to memset(p,0,n) and the current use of
On 2024-11-26 10:58, Jan Beulich wrote:
On 26.11.2024 10:35, Roger Pau Monne wrote:
The current guards to select whether user accesses should be
speculative
hardened violate Misra rule 20.7, as the UA_KEEP() macro doesn't (and
can't)
parenthesize the 'args' argument.
For my own education: Th
On Tue, 2024-11-26 at 15:21 -0800, Denis Mukhin via B4 Relay wrote:
> From: Denis Mukhin
>
> Introduce domain_has_vuart() for RISC-V port to be used in the
> console driver.
>
> Signed-off-by: Denis Mukhin
> ---
> xen/arch/riscv/include/asm/domain.h | 2 ++
> 1 file changed, 2 insertions(+)
>
Hi Michal,
On Wed, Nov 27, 2024 at 11:48 AM Michal Orzel wrote:
> On 19/11/2024 15:13, Carlo Nonato wrote:
> >
> >
> > Last Level Cache (LLC) coloring allows to partition the cache in smaller
> > chunks called cache colors.
> >
> > Since not all architectures can actually implement it, add a
> >
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