microcode_update{,_helper}() are overly generic names in a file that has
multiple update routines and helper functions contexts.
Rename microcode_update() to ucode_update_hcall() so it explicitly identifies
itself as hypercall context, and rename microcode_update_helper() to
ucode_update_hcall_con
Hi,
On 24/10/2024 09:02, Ayan Kumar Halder wrote:
On 23/10/2024 17:30, Julien Grall wrote:
On 23/10/2024 17:18, Julien Grall wrote:
On 23/10/2024 17:13, Julien Grall wrote:
On 23/10/2024 17:06, Ayan Kumar Halder wrote:
Hi Luca/Julien,
On 22/10/2024 17:31, Luca Fancellu wrote:
Hi Juli
In PVH dom0, when passthrough a device to domU, QEMU code
xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes
the gsi number is got from file /sys/bus/pci/devices//irq, that is
wrong, because irq is not equal with gsi, they are in different spaces, so
pirq mapping fails.
To
Acked-by: Simon Ser
On Wed, Oct 02, 2024 at 09:21:58PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> An attempt to hide the drm_plane/crtc legacy state better.
>
> This also highlights the fact that a lot of supposedly
> atomic drivers are poking around in the legacy crtc state,
> which is rather questionab
On Thu, 24 Oct 2024 10:02:59 +0200,
Philipp Stanner wrote:
>
> On Wed, 2024-10-23 at 17:03 +0200, Takashi Iwai wrote:
> > On Wed, 23 Oct 2024 15:50:09 +0200,
> > Philipp Stanner wrote:
> > >
> > > On Tue, 2024-10-22 at 16:08 +0200, Takashi Iwai wrote:
> > > > On Tue, 15 Oct 2024 20:51:12 +0200,
>
cpu_request_microcode() was never a good name, and the microcode suffix is
redundant. Rename it to simply parse().
Introduce ucode_parse() and ucode_parse_dup() wrappers around the parse()
hook, also abstracting away the make_copy parameter and associated
const-correctness.
No functional change.
This prevents the reintroduction of patterns which turn out to be unsafe for
PVH boots. Various bits extracted/rearranged from the Hyperlaunch v7 series.
https://gitlab.com/xen-project/people/andyhhp/xen/-/pipelines/1509397930
Andrew Cooper (2):
x86/boot: Introduce bootstrap_unmap()
x86/boot
Hi Bertrand,
On Wed, Oct 16, 2024 at 10:32 AM Bertrand Marquis
wrote:
>
> Remove the per VM flag to store if notifications are enabled or not as
> the only case where they are not, if notifications are enabled globally,
> will make the VM creation fail.
> Also use the opportunity to always give t
On 24.10.24 15:35, Daniel P. Smith wrote:
On 10/24/24 05:13, Jürgen Groß wrote:
On 23.10.24 17:55, Daniel P. Smith wrote:
On 10/23/24 09:10, Juergen Gross wrote:
Add a new domctl sub-function to get data of a domain having changed
state (this is needed by Xenstore).
The returned state just co
On Thu, 24 Oct 2024, Ryan Roberts wrote:
> On 23/10/2024 02:23, Stefano Stabellini wrote:
> > +Julien
> >
> > On Wed, 16 Oct 2024, Ryan Roberts wrote:
> >> + Juergen Gross, Stefano Stabellini
> >>
> >> This was a rather tricky series to get the recipients correct for and my
> >> script
> >> did n
On Thu, 2024-10-24 at 17:43 +0200, Takashi Iwai wrote:
> On Thu, 24 Oct 2024 10:02:59 +0200,
> Philipp Stanner wrote:
> >
> > On Wed, 2024-10-23 at 17:03 +0200, Takashi Iwai wrote:
> > > On Wed, 23 Oct 2024 15:50:09 +0200,
> > > Philipp Stanner wrote:
> > > >
> > > > On Tue, 2024-10-22 at 16:08 +
When using AMD-VI interrupt remapping the vector field in the IO-APIC RTE is
repurposed to contain part of the offset into the remapping table. Previous to
2ca9fbd739b8 Xen had logic so that the offset into the interrupt remapping
table would match the vector. Such logic was mandatory for end of
Split report_syscall() to two separate enter and exit
functions. So it will be more clear when arm64 switch to
generic entry.
No functional changes.
Suggested-by: Mark Rutland
Signed-off-by: Jinjie Ruan
---
arch/arm64/kernel/ptrace.c | 29 -
1 file changed, 20 inser
On 25/10/2024 10:50 am, Carlo Nonato wrote:
> SUPPORT.md| 7 ++
> docs/misc/cache-coloring.rst | 116 ++
> docs/misc/xen-command-line.pandoc | 37 ++
> xen/common/Kconfig| 22 ++
> xen/common/Makefile
On 24/10/2024 4:10 pm, Javi Merino wrote:
> On Thu, Oct 24, 2024 at 03:04:10PM +0100, Andrew Cooper wrote:
>> On 24/10/2024 11:04 am, Javi Merino wrote:
>>> +
>>> +apt-get update
>> apt-get -y
> apt-get update refreshes the package lists. -y doesn't do anything
> here. It is needed for "apt-g
Add a new "llc_colors" parameter that defines the LLC color assignment for
a domain. The user can specify one or more color ranges using the same
syntax used everywhere else for color config described in the
documentation.
The parameter is defined as a list of strings that represent the color
range
Cache coloring requires Dom0 not to be direct-mapped because of its non
contiguous mapping nature, so allocate_memory() is needed in this case.
8d2c3ab18cc1 ("arm/dom0less: put dom0less feature code in a separate module")
moved allocate_memory() in dom0less_build.c. In order to use it
in Dom0 const
Last Level Cache (LLC) coloring allows to partition the cache in smaller
chunks called cache colors.
Since not all architectures can actually implement it, add a HAS_LLC_COLORING
Kconfig option.
MAX_LLC_COLORS_ORDER Kconfig option has a range maximum of 10 (2^10 = 1024)
because that's the number o
Add a new memory page allocator that implements the cache coloring mechanism.
The allocation algorithm enforces equal frequency distribution of cache
partitions, following the coloring configuration of a domain. This allows
for an even utilization of cache sets for every domain.
Pages are stored i
Add the cache coloring support for Xen physical space.
Since Xen must be relocated to a new physical space, some relocation
functionalities must be brought back:
- the virtual address of the new space is taken from 0c18fb76323b
("xen/arm: Remove unused BOOT_RELOC_VIRT_START").
- relocate_xen() a
Shared caches in multi-core CPU architectures represent a problem for
predictability of memory access latency. This jeopardizes applicability
of many Arm platform in real-time critical and mixed-criticality
scenarios. We introduce support for cache partitioning with page
coloring, a transparent sof
Add a command line parameter to allow the user to set the coloring
configuration for Dom0.
A common configuration syntax for cache colors is introduced and
documented.
Take the opportunity to also add:
- default configuration notion.
- function to check well-formed configurations.
Direct mapping
Add the "llc-colors" Device Tree attribute to express DomUs and Dom0less
color configurations.
Based on original work from: Luca Miccio
Signed-off-by: Carlo Nonato
Signed-off-by: Marco Solieri
---
v9:
- use best-effort allocation in domain_set_llc_colors_from_str()
v8:
- fixed memory leak on e
LLC coloring needs to know the last level cache layout in order to make the
best use of it. This can be probed by inspecting the CLIDR_EL1 register,
so the Last Level is defined as the last level visible by this register.
Note that this excludes system caches in some platforms.
Static memory alloc
Cache colored domains can benefit from having p2m page tables allocated
with the same coloring schema so that isolation can be achieved also for
those kind of memory accesses.
In order to do that, the domain struct is passed to the allocator and the
MEMF_no_owner flag is used.
This will be useful
Cache coloring must physically relocate Xen in order to color the hypervisor
and consider_modules() is a key function that is needed to find a new
available physical address.
672d67f339c0 ("xen/arm: Split MMU-specific setup_mm() and related code out")
moved consider_modules() under arm32. Move it
On 2024-10-24 09:22, Andrew Cooper wrote:
The microcode suffix is redundant, and "microcode loading" is the more common
term
Missing your S-o-B.
With that:
Reviewed-by: Jason Andryuk
On 2024-10-24 09:22, Andrew Cooper wrote:
This was true in the K10 days, but even back then the match registers were
really payload data rather than header data.
But, it's really model specific data, and these days typically part of the
signature, so is random data for all intents and purposes.
This was true in the K10 days, but even back then the match registers were
really payload data rather than header data.
But, it's really model specific data, and these days typically part of the
signature, so is random data for all intents and purposes.
No functional change.
Signed-off-by: Andre
"xen/arch/arm/include/asm/tee" is a directory and should be terminated
by a slash ("/").
Signed-off-by: Frediano Ziglio
Acked-by: Julien Grall
Acked-by: Volodymyr Babchuk
Acked-by: Bertrand Marquis
---
Changes since v1:
- removed second change, it was intentional.
Changes since v2:
- rebase o
Add a new domctl hypercall to allow the user to set LLC coloring
configurations. Colors can be set only once, just after domain creation,
since recoloring isn't supported.
Based on original work from: Luca Miccio
Signed-off-by: Carlo Nonato
Signed-off-by: Marco Solieri
Reviewed-by: Jan Beulich
From: Luca Miccio
Add a new command line parameter to configure Xen cache colors.
These colors are dumped together with other coloring info.
Benchmarking the VM interrupt response time provides an estimation of
LLC usage by Xen's most latency-critical runtime task. Results on Arm
Cortex-A53 on X
On Fri, 25 Oct 2024 at 10:46, Ville Syrjälä
wrote:
>
> On Wed, Oct 02, 2024 at 09:21:58PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > An attempt to hide the drm_plane/crtc legacy state better.
> >
> > This also highlights the fact that a lot of supposedly
> > atomic drivers are po
On Fri, 25 Oct 2024, Ville Syrjälä wrote:
> On Wed, Oct 02, 2024 at 09:21:58PM +0300, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> An attempt to hide the drm_plane/crtc legacy state better.
>>
>> This also highlights the fact that a lot of supposedly
>> atomic drivers are poking around in
Move arm64_preempt_schedule_irq() into exit_to_kernel_mode(), so not
only __el1_irq() but also every time when kernel mode irq return,
there is a chance to reschedule.
As Mark pointed out, this change will have the following key impact:
"We'll preempt even without taking a "real" interrupt. T
Rework arm64_preempt_schedule_irq() to check whether it need
resched in a check function arm64_irqentry_exit_need_resched().
No functional changes.
Signed-off-by: Jinjie Ruan
---
arch/arm64/kernel/entry-common.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --gi
Extract the arm64 resched logic code to
raw_irqentry_exit_cond_resched() function, which makes the
code more clear when switch to generic entry.
No functional changes.
Signed-off-by: Jinjie Ruan
---
arch/arm64/include/asm/preempt.h | 1 +
arch/arm64/kernel/entry-common.c | 17 ++---
Check dynamic key ahead in raw_irqentry_exit_cond_resched(), which
will make arm64_irqentry_exit_need_resched() all about arch-specific.
No functional changes.
Signed-off-by: Jinjie Ruan
---
arch/arm64/kernel/entry-common.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
The __enter_from_user_mode() is only called by enter_from_user_mode(),
so replaced it with enter_from_user_mode().
No functional changes.
Signed-off-by: Jinjie Ruan
---
arch/arm64/kernel/entry-common.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm64/kernel/e
The __enter_from_kernel_mode() is only called by enter_from_kernel_mode(),
remove it.
No functional changes.
Signed-off-by: Jinjie Ruan
---
arch/arm64/kernel/entry-common.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/
Implement regs_irqs_disabled(), and replace interrupts_enabled() macro
with regs_irqs_disabled() all over the place.
No functional changes.
Suggested-by: Mark Rutland
Signed-off-by: Jinjie Ruan
---
arch/arm/include/asm/ptrace.h | 4 ++--
arch/arm/kernel/hw_breakpoint.c | 2 +-
arch/a
Whether PREEMPT_DYNAMIC enabled or not, PREEMPTION should
be enabled to allow reschedule after an interrupt.
Signed-off-by: Jinjie Ruan
---
arch/arm64/kernel/entry-common.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm
__exit_to_kernel_mode() is only called by exit_to_kernel_mode(),
remove it.
No functional changes.
Signed-off-by: Jinjie Ruan
---
arch/arm64/kernel/entry-common.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kern
Check dynamic resched alone when PREEMPT_DYNAMIC enabled.
No functional changes.
Signed-off-by: Jinjie Ruan
---
arch/arm64/include/asm/preempt.h | 3 +++
arch/arm64/kernel/entry-common.c | 21 +++--
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/inc
The "READ_ONCE(current_thread_info()->preempt_count = 0" is equivalent
to "preempt_count() == 0 && need_resched()", so use these helpers to
replace it, which will make it more clear when switch to generic entry.
No functional changes.
Signed-off-by: Jinjie Ruan
---
arch/arm64/kernel/entry-commo
Only if irqs are enabled when the interrupt trapped, there may be
a chance to reschedule after the interrupt has been handled, so move
arm64_preempt_schedule_irq() into regs_irqs_disabled() check false
if block.
As Mark pointed out, this change will have the following key impact:
"We will not
Add some syscall arch functions to support arm64 to use generic syscall
code, which do not affect existing architectures that use generic entry:
- arch_pre/post_report_syscall_entry/exit().
Also make syscall_exit_work() not static and move report_single_step() to
thread_info.h, which can be used
Currently, x86, Riscv, Loongarch use the generic entry. Convert arm64
to use the generic entry infrastructure from kernel/entry/*. The generic
entry makes maintainers' work easier and codes more elegant, which aslo
removed a lot of duplicate code.
The patch 1 ~ 5 try to make arm64 easier to use ir
On Thu Oct 24, 2024 at 2:22 PM BST, Andrew Cooper wrote:
> Misc cleanup without functional change. Mostly to improve clarity.
>
> Andrew Cooper (5):
> x86/ucode: Rename hypercall-context functions
> x86/ucode: Drop the parse_blob() wrapper
> x86/ucode: Rename the cpu_request_microcode() hook
These changes refactor the entry and exit routines for the exceptions
from EL1. They store the RCU and lockdep state in a struct
irqentry_state variable on the stack, rather than recording them
in the fields of pt_regs, since it is safe enough for these context.
Before:
struct pt_regs {
As the front patch 6 ~ 13 did, the arm64_preempt_schedule_irq() is
same with the irq preempt schedule code of generic entry besides those
architecture-related logic called arm64_irqentry_exit_need_resched().
So add arch irqentry_exit_need_resched() to support architecture-related
need_resched() ch
Currently, x86, Riscv, Loongarch use the generic entry. Convert arm64
to use the generic entry infrastructure from kernel/entry/*.
The generic entry makes maintainers' work easier and codes
more elegant.
Switch arm64 to generic IRQ entry first, which removed duplicate 100+ LOC,
the next patch will
As Mark pointed out, do not try to switch to *all* the
generic entry code in one go. The regular entry state management
(e.g. enter_from_user_mode() and exit_to_user_mode()) is largely
separate from the syscall state management. Move arm64 over to
enter_from_user_mode() and exit_to_user_mode() with
Currently, x86, Riscv, Loongarch use the generic entry. Convert arm64
to use the generic entry infrastructure from kernel/entry/*.
The generic entry makes maintainers' work easier and codes more elegant.
The changes are below:
- Remove TIF_SYSCALL_* flag, _TIF_WORK_MASK, _TIF_SYSCALL_WORK
- Remo
On 2024-10-24 09:22, Andrew Cooper wrote:
microcode_update{,_helper}() are overly generic names in a file that has
multiple update routines and helper functions contexts.
Rename microcode_update() to ucode_update_hcall() so it explicitly identifies
itself as hypercall context, and rename microco
On 2024-10-24 09:22, Andrew Cooper wrote:
This separates the collect_cpu_info() and cpu_request_microcode() calls for
later cleanup, and frees up the name to be reused a little differently.
No functional change.
Signed-off-by: Andrew Cooper
Reviewed-by: Jason Andryuk
On 2024-10-24 09:22, Andrew Cooper wrote:
cpu_request_microcode() was never a good name, and the microcode suffix is
redundant. Rename it to simply parse().
Introduce ucode_parse() and ucode_parse_dup() wrappers around the parse()
hook, also abstracting away the make_copy parameter and associat
PGC_static and PGC_extra needs to be preserved when assigning a page.
Define a new macro that groups those flags and use it instead of or'ing
every time.
To make preserved flags even more meaningful, they are kept also when
switching state in mark_page_free().
Enforce the removal of PGC_extra befo
url:
> https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-remove-driver-date-from-struct-drm_driver-and-all-drivers/20241025-002344
> base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
> patch link:
> https://lore.kernel.org/r/20241024162240.2398664-2-jan
On Fri, 25 Oct 2024 10:37:57 +0200,
Philipp Stanner wrote:
>
> On Thu, 2024-10-24 at 17:43 +0200, Takashi Iwai wrote:
> > On Thu, 24 Oct 2024 10:02:59 +0200,
> > Philipp Stanner wrote:
> > >
> > > On Wed, 2024-10-23 at 17:03 +0200, Takashi Iwai wrote:
> > > > On Wed, 23 Oct 2024 15:50:09 +0200,
>
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