> On 8. Feb 2018, at 18:24, Wei Liu wrote:
>
> Christian, do you have any idea when you can look into fixing the
> safe-string patch?
Sorry, I can’t make a promise because of my other obligations. I do wonder,
though: this patch did not come out of nowhere but supposedly was working -
what i
On Fri, 2018-02-09 at 09:20 +, Christian Lindig wrote:
> > On 8. Feb 2018, at 18:24, Wei Liu wrote:
> >
> > Christian, do you have any idea when you can look into fixing the
> > safe-string patch?
>
> Sorry, I can’t make a promise because of my other obligations. I do
> wonder, though: this
On Thu, Feb 8, 2018 at 3:25 PM, Alexandru Isaila
wrote:
> This commit separates the svm caps from the vmx caps.
I can see how the patch relates to the description here, but it's not
immediately clear how it relates to the title.
A good "template" to start with for any commit message is:
1. What
On Thu, Feb 08, 2018 at 08:10:49PM -0700, Sameer Goel wrote:
> diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
> index 1d9771340c..697212a061 100644
> --- a/xen/include/xen/lib.h
> +++ b/xen/include/xen/lib.h
> @@ -11,6 +11,19 @@
> #define BUG_ON(p) do { if (unlikely(p)) BUG(); } whil
On Thu, Feb 8, 2018 at 3:25 PM, Alexandru Isaila
wrote:
> This commit enables the breakpoint events for svm.
s/enable/implement/;
-George
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flight 118670 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/118670/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt-xsm 14 saverestore-support-checkfail like 118630
test-armhf-armhf-libvirt 14 sav
On Thu, Feb 8, 2018 at 3:25 PM, Alexandru Isaila
wrote:
> This commit enables MSR events for svm.
I'd probably say 'implement' here as well.
Also, you don't need to repeat the title in the commit message. If
there's nothing more to put into the commit message than is said in
the title, you can
On Thu, Feb 08, 2018 at 08:10:54PM -0700, Sameer Goel wrote:
> Pull common defines for SMMU drives in a local header.
>
> Signed-off-by: Sameer Goel
> ---
> xen/drivers/passthrough/arm/arm_smmu.h | 125
> +
> xen/drivers/passthrough/arm/smmu-v3.c | 96 +
Hi,
On 02/09/2018 10:29 AM, Roger Pau Monné wrote:
On Thu, Feb 08, 2018 at 08:10:49PM -0700, Sameer Goel wrote:
diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
index 1d9771340c..697212a061 100644
--- a/xen/include/xen/lib.h
+++ b/xen/include/xen/lib.h
@@ -11,6 +11,19 @@
#define BUG
On Fri, Feb 09, 2018 at 10:45:25AM +, Julien Grall wrote:
> Hi,
>
> On 02/09/2018 10:29 AM, Roger Pau Monné wrote:
> > On Thu, Feb 08, 2018 at 08:10:49PM -0700, Sameer Goel wrote:
> > > diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
> > > index 1d9771340c..697212a061 100644
> > > -
Hi,
On 02/09/2018 10:43 AM, Roger Pau Monné wrote:
+unsigned int type;
+};
+
+#define resource_size(res) ((res)->size)
+
+#define platform_device device
+
+#define IORESOURCE_MEM 0
+#define IORESOURCE_IRQ 1
+
+/* Stub out DMA domain related functions */
+#define iommu_get_dma_cookie(dom) 0
+
On Fri, Feb 9, 2018 at 10:28 AM, George Dunlap wrote:
> On Thu, Feb 8, 2018 at 3:25 PM, Alexandru Isaila
> wrote:
>> This commit separates the svm caps from the vmx caps.
>
> I can see how the patch relates to the description here, but it's not
> immediately clear how it relates to the title.
>
>
On Fri, Feb 09, 2018 at 02:02:42AM +0100, Marek Marczykowski-Górecki wrote:
> Hi,
>
> I'd like to avoid calling block script to speed up domain startup a
> little (there may be multiple disks, all already being block devices).
> Right now I have restored setting physical-device xenstore entry in
>
The emulation layers of Xen lack PCID support, and as we only offer
PCID to HAP guests, all writes to CR3 are handled by hardware,
except when introspection is involved. Consequently, trying to set
CR3 when the noflush bit is set in hvm_set_cr3() leads to domain
crashes. The workaround is to clear
On Vi, 2018-02-09 at 10:37 +, George Dunlap wrote:
> On Thu, Feb 8, 2018 at 3:25 PM, Alexandru Isaila
> wrote:
> >
> > This commit enables MSR events for svm.
> I'd probably say 'implement' here as well.
>
> Also, you don't need to repeat the title in the commit message. If
> there's nothing
On Fri, Feb 09, 2018 at 10:51:01AM +, Julien Grall wrote:
> Hi,
>
> On 02/09/2018 10:43 AM, Roger Pau Monné wrote:
> > > +unsigned int type;
> > > +};
> > > +
> > > +#define resource_size(res) ((res)->size)
> > > +
> > > +#define platform_device device
> > > +
> > > +#define IORESOURCE_MEM
Really adding Ian and Wei.
On Fri, Feb 09, 2018 at 10:55:24AM +, Roger Pau Monné wrote:
> On Fri, Feb 09, 2018 at 02:02:42AM +0100, Marek Marczykowski-Górecki wrote:
> > Hi,
> >
> > I'd like to avoid calling block script to speed up domain startup a
> > little (there may be multiple disks, al
Hi,
On 02/09/2018 11:02 AM, Roger Pau Monné wrote:
On Fri, Feb 09, 2018 at 10:51:01AM +, Julien Grall wrote:
Hi,
On 02/09/2018 10:43 AM, Roger Pau Monné wrote:
+unsigned int type;
+};
+
+#define resource_size(res) ((res)->size)
+
+#define platform_device device
+
+#define IORESOURCE_M
On Fri, Feb 09, 2018 at 12:22:13AM +0100, Marek Marczykowski-Górecki wrote:
> Backend domain may be independently destroyed - there is no
> synchronization of libxl structures (including /libxl tree) elsewhere.
> Backend might also remove the device info from its backend xenstore
> subtree on its o
On Fri, Feb 09, 2018 at 11:03:55AM +, Roger Pau Monné wrote:
> Really adding Ian and Wei.
>
> On Fri, Feb 09, 2018 at 10:55:24AM +, Roger Pau Monné wrote:
> > So the problem is creation time for domains that have quite a lot of
> > disks attached. Adding Ian and Wei who know more about the
On Fri, Feb 09, 2018 at 12:14:03AM +0100, Marek Marczykowski-Górecki wrote:
> When fd=-1, no savefile will be written, but the domain will still be
> suspended (but not destroyed). The main reason for this functionality is
> to suspend the host while some domains are running, potentially holding
>
On Fri, Feb 09, 2018 at 11:27:04AM +, Roger Pau Monné wrote:
> On Fri, Feb 09, 2018 at 12:22:13AM +0100, Marek Marczykowski-Górecki wrote:
> > Backend domain may be independently destroyed - there is no
> > synchronization of libxl structures (including /libxl tree) elsewhere.
> > Backend might
On Thu, Feb 08, 2018 at 10:49:08PM +0100, Simon Gaiser wrote:
> xc_dom_loader.parser() should return elf_negerrnoval.
>
> Signed-off-by: Simon Gaiser
LGTM:
Reviewed-by: Roger Pau Monné
Thanks.
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On Thu, Feb 08, 2018 at 10:49:09PM +0100, Simon Gaiser wrote:
> xc_dom_parse_image() does not set errno (at least in many code paths).
> So LOGE() is not useful.
IIRC the expectation is that libxc functions will return -1 on failure
and set errno. This is however far from true, so:
> Signed-off-b
On Fri, Feb 09, 2018 at 12:41:58PM +0100, Marek Marczykowski-Górecki wrote:
> On Fri, Feb 09, 2018 at 11:27:04AM +, Roger Pau Monné wrote:
> > I'm also wondering, if you jump to 'out' here, you avoid the call to
> > libxl__xs_transaction_commit and instead end up calling
> > libxl__xs_transacti
On Thu, Feb 08, 2018 at 10:49:10PM +0100, Simon Gaiser wrote:
> Commit 96edb111dd ("libxc: panic when trying to create a PVH guest
> without kernel support") already improved the handling of non PVH
> capable kernels. But xc_dom_parse_elf_kernel() still returned success on
> invalid elf images and
Dear Dario,
Now I'm experimenting with RTDS, in particular with "extra time"
functionality.
My experimental setup is built on Salvator-X board with H3 SOC (running
only big cores cluster, 4xA57).
Domains up and running, and their VCPU are as following:
root@generic-armv8-xt-dom0:/xt/dom.cfg
Hello Dario,
I eventually used your old email.
Please take a look here.
On 09.02.18 14:20, Andrii Anisov wrote:
Dear Dario,
Now I'm experimenting with RTDS, in particular with "extra time"
functionality.
My experimental setup is built on Salvator-X board with H3 SOC
(running only big co
Thanks for the series, I'm however wondering whether it's appropriate
to post a v4 as RFC. Ie: at v4 the reviewer expects the submitter to
have a clear picture of what needs to be implemented.
On Thu, Dec 07, 2017 at 06:09:49PM +0800, Haozhong Zhang wrote:
> All patches can also be found at
> Xe
On 30/01/18 16:40, Jan Beulich wrote:
On 22.01.18 at 13:32, wrote:
>> @@ -37,10 +52,24 @@ struct vcpu;
>>
>> struct cpu_info {
>> struct cpu_user_regs guest_cpu_user_regs;
>> -unsigned int processor_id;
>> -struct vcpu *current_vcpu;
>> -unsigned long per_cpu_offset;
>> -
Hi Julien,
On 8 February 2018 at 20:12, Julien Grall wrote:
Currently, the behavior of do_common_cpu will slightly change depending
>>> on the PSCI version passed in parameter. Looking at the code, more the
>>> specific 0.2 behavior could move out of the function or adapted for 0.1:
>>>
>>>
On Fri, Nov 17, 2017 at 02:22:08PM +0800, Chao Gao wrote:
> From: Lan Tianyu
>
> This patch is to add Xen virtual IOMMU doc to introduce motivation,
> framework, vIOMMU hypercall and xl configuration.
>
> Signed-off-by: Lan Tianyu
> Signed-off-by: Chao Gao
> ---
> docs/misc/viommu.txt | 120
On Mon, Feb 5, 2018 at 4:14 PM, Andrew Cooper wrote:
> On 05/02/18 15:03, Arnd Bergmann wrote:
>
> Snipping deleted code to make things clearer:
>
>> + if (cmd > ARRAY_SIZE(physdevop_len))
>> + return -ENOSYS;
>>
>> + len = physdevop_len[cmd];
>> + memcpy(&op.u, arg, len);
On Fri, Feb 09, 2018 at 12:10:39PM +, Roger Pau Monné wrote:
> On Fri, Feb 09, 2018 at 12:41:58PM +0100, Marek Marczykowski-Górecki wrote:
> > On Fri, Feb 09, 2018 at 11:27:04AM +, Roger Pau Monné wrote:
> > > I'm also wondering, if you jump to 'out' here, you avoid the call to
> > > libxl_
On Jo, 2018-02-08 at 11:06 -0700, Tamas K Lengyel wrote:
> On Thu, Feb 8, 2018 at 8:25 AM, Alexandru Isaila
> wrote:
> >
> > This commit enables controlregister events for svm.
> So this patch enables the event to trigger but where is it being
> handled and forwarded to the monitor ring?
Hi Tamas,
On Fri, 2018-02-09 at 14:20 +0200, Andrii Anisov wrote:
> Dear Dario,
>
Hi,
> My experimental setup is built on Salvator-X board with H3 SOC
> (running
> only big cores cluster, 4xA57).
> Domains up and running, and their VCPU are as following:
>
> root@generic-armv8-xt-dom0:/xt/dom.cfg# xl sch
This patch series is meant to be used instead of the "XPTI-light"
Meltdown mitigation of Jan. It is using a different approach by
using a shadow of the guest's L4 page table and keeping those in a
cache in order to avoid the need to create the shadow multiple
times. I'll name my approach "XPTI" in
In case of XPTI being active for a pv-domain allocate and initialize
per-vcpu stacks. The stacks are added to the per-domain mappings of
the pv-domain.
Signed-off-by: Juergen Gross
---
V3:
- move xpti code to xpti.c
- directly modify page table entries as needed for stub and stack
page (Jan Beu
In order to support switching stacks when entering the hypervisor for
support of page table isolation, don't use %rsp for accessing the
saved user registers, but do that via %r12.
Signed-off-by: Juergen Gross
---
V3:
- use %r12 instead %rdi (Jan Beulich)
- remove some compat changes (Jan Beulich)
show_guest_stack() and compat_show_guest_stack() stop dumping the
stack of the guest whenever its virtual address reaches the same
alignment which is used for the hypervisor stacks.
Remove this arbitrary limit and try to dump a fixed number of lines
instead.
Signed-off-by: Juergen Gross
---
xen
Modify the interrupt handlers to switch stacks on interrupt entry in
case they are running on a per-vcpu stack. Same applies to returning
to the guest: in case the to be loaded context is located on a
per-vcpu stack switch to this one before returning to the guest.
The NMI and MCE interrupt handle
Revert patch "x86: Meltdown band-aid against malicious 64-bit PV
guests" in order to prepare for a final Meltdown mitigation.
Signed-off-by: Juergen Gross
---
xen/arch/x86/domain.c | 5 -
xen/arch/x86/mm.c | 21
xen/arch/x86/smpboot.c | 200 -
When scheduling a vcpu subject to xpti activate the per-vcpu stacks
by loading the vcpu specific gdt and tss. When de-scheduling such a
vcpu switch back to the per physical cpu gdt and tss.
Accessing the user registers on the stack is done via helpers as
depending on XPTI active or not the registe
When XPTI for a domain is switched on allocate a hypervisor L4 page
table for each guest L4 page table. For performance reasons keep a
cache of the last used hypervisor L4 pages with the maximum number
depending on the number of vcpus of the guest.
Signed-off-by: Juergen Gross
---
xen/arch/x86/m
Revert "x86: allow Meltdown band-aid to be disabled" in order to
prepare for a final Meltdown mitigation.
Signed-off-by: Juergen Gross
---
docs/misc/xen-command-line.markdown | 12
xen/arch/x86/domain.c | 7 ++-
xen/arch/x86/mm.c | 12 +--
For XPTI enabled domains do page table switching when entering or
leaving the hypervisor. This requires both %cr3 values to be stored
in the per-vcpu stack regions and adding the switching code to the
macros used to switch stacks.
The hypervisor will run on the original L4 page table supplied by t
In order to be able to sync L4 page table modifications with XPTI we
need the domain pointer in fill_ro_mpt() and zap_ro_mpt().
Signed-off-by: Juergen Gross
---
xen/arch/x86/domain.c | 6 +++---
xen/arch/x86/mm.c | 8
xen/arch/x86/mm/shadow/multi.c | 4 ++--
xen/in
For being able to use the XPTI shadow L4 page tables in the hypervisor
fill them with the related entries of their masters and keep them in
sync when updates are done by the guest.
Signed-off-by: Juergen Gross
---
xen/arch/x86/mm.c | 43 ++
xe
_set_tssldt_desc() is used to set LDT or TSS descriptors in the GDT.
As LDT descriptors might be shared across cpus care is taken to not
create a temporary invalid descriptor.
Split _set_tssldt_desc() into dedicated functions for setting either
a LDT or a TSS descriptor. For LDT descriptors this i
Add a command line parameter for controlling Xen page table isolation
(XPTI): per default it is on for non-AMD systems in 64 bit pv domains.
Possible settings are:
- true: switched on even on AMD systems
- false: switched off for all
- nodom0: switched off for dom0
As we don't want to set XPTI fo
Hide all but the absolute necessary hypervisor mappings in the XPTI
shadow page tables. The following mappings are needed:
- guest accessible areas, e.g. the RO M2P table
- IDT, TSS, GDT
- interrupt entry stacks
- interrupt handling code
For some of those mappings we need to setup lower level pag
The current syscall stub can't be used mapped in the per domain area
as required by XPTI due to the distance for jumping into the common
interrupt handling code is larger than 2GB. Using just an indirect
jump isn't going to work as this will require mitigations against
Spectre.
So use a new trampo
For support of per-vcpu stacks we need per-vcpu trampolines. To be
able to put those into the per-domain mappings the upper levels
page tables must not have NX set for per-domain mappings.
As create_perdomain_mapping() creates L1 mappings with flags being
__PAGE_HYPERVISOR_RW this won't change any
Right now an indirect jump might use a relative jump to a retpoline
thunk in order to mitigate the Spectre vulnerability.
In case the code using the indirect jump is remapped to another
virtual address this won't work any longer, so add support for
indirect jumps using a local thunk instead.
Sign
From: Arnd Bergmann
> Sent: 09 February 2018 12:58
...
> However, aside from this driver, I wonder if we should be worried about
> Spectre type 1 attacks on similar code, when gcc-8 turns a switch/case
> statement into an array lookup behind our back, e.g. in an ioctl handler.
> Has anybody got thi
On Fri, Feb 9, 2018 at 3:13 PM, David Laight wrote:
> From: Arnd Bergmann
>> Sent: 09 February 2018 12:58
> ...
>> However, aside from this driver, I wonder if we should be worried about
>> Spectre type 1 attacks on similar code, when gcc-8 turns a switch/case
>> statement into an array lookup beh
Linus,
Please git pull the following tag:
git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git
for-linus-4.16-rc1-tag
xen: fixes for 4.16 rc1
This time only 5 small fixes for issues when running under Xen.
Thanks.
Juergen
arch/x86/xen/p2m.c | 6 ++
arch/x86/xen/xen-head
On Fri, Nov 17, 2017 at 02:22:09PM +0800, Chao Gao wrote:
> From: Lan Tianyu
>
> This patch is to introduce an abstract layer for arch vIOMMU implementation
> and vIOMMU domctl to deal with requests from tool stack. Arch vIOMMU code
> needs to
> provide callback. vIOMMU domctl supports to create
tl;dr: More preparatory patches from patch 07, actual new VGIC starting
at patch 20.
=
During development of the Dom0 ITS MSI support last year we realised
that the existing GIC interrupt controller emulation has some shortcomings.
After some tries to fix those in the existing code, it
The last patch removed the usage of the hardware's redistributor-stride
value from our (Dom0) GICv3 emulation. This means we no longer need to
store this value in the VGIC data structure.
Remove that variable and every code snippet that handled that, instead
simply always use the architected value.
On Fri, Feb 09, 2018 at 02:08:33PM +0100, Marek Marczykowski-Górecki wrote:
> On Fri, Feb 09, 2018 at 12:10:39PM +, Roger Pau Monné wrote:
> > On Fri, Feb 09, 2018 at 12:41:58PM +0100, Marek Marczykowski-Górecki wrote:
> > > On Fri, Feb 09, 2018 at 11:27:04AM +, Roger Pau Monné wrote:
> > >
Architecturally there is only one GICv3 redistributor region.
Drop the symbol which suggested that was a delibarate choice for Xen
guests, instead hard code the "1" in the appropriate places, along with
a comment to explain the reasons.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic-v3.c
So far the number of list registers (LRs) a GIC implements is only
needed in the hardware facing side of the VGIC code (gic-vgic.c).
The new VGIC will need this information in more and multiple places, so
export a function that returns the number.
Signed-off-by: Andre Przywara
---
xen/arch/arm/g
At the moment vgic_vcpu_inject_irq() is the interface for Xen internal
code and virtual devices to inject IRQs into a guest. This interface has
two shortcomings:
1) It requires a VCPU pointer, which we may not know (and don't need!)
for shared interrupts. A second function (vgic_vcpu_inject_spi()),
Currently we describe the VGIC specific fields in an structure
*embedded* in struct arch_domain and struct arch_vcpu. These members
there are however related to the current VGIC implementation, and will
be substantially different in the future.
To allow coexistence of two implementations, move the
The redistributor-stride property in a GICv3 DT node is only there to
cover broken platforms where this value deviates from the architected one.
Since we emulate the GICv3 distributor even for Dom0, we don't need to
copy the broken behaviour. All the special handling for Dom0s using
GICv3 is just f
To synchronize level triggered interrupts which are mapped into a guest,
we need to update the virtual line level at certain points in time.
For a hardware mapped interrupt the GIC is the only place where we can
easily access this information.
Implement a gic_hw_operations member to return the pend
The code to generate the DT node or MADT table for Dom0 reaches into the
domain's VGIC structure to learn the number of redistributor regions and
their base addresses.
Since those values are copied from the hardware, we can as well use
those hardware values directly when setting up the hardware dom
The new VGIC will shortly use more bits of the GICC_CTLR register, so
add the respective definitions from the manual.
Also add a missing definition for GICV_PMR_PRIORITY_MASK.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v2.c | 2 +-
xen/include/asm-arm/gic.h | 18 --
The event channel IRQ has level triggered semantics, however the current
VGIC treats everything as edge triggered.
To correctly process those IRQs, we have to lower the (virtual) IRQ line
at some point in time, depending on whether ther interrupt condition
still prevails.
Check the per-VCPU evtchn_
The ARM Generic Timer uses a level-sensitive interrupt semantic. We
easily catch when the line goes high, as this triggers the hardware IRQ.
However we have to sync the state of the interrupt condition at certain
points to catch when the line goes low and we can remove the vtimer vIRQ
from the vGIC
Those three registers are v2 emulation specific, so their implementation
lives entirely in vgic-mmio-v2.c. Also they are handled in one function,
as their implementation is pretty simple.
When the guest enables the distributor, we kick all VCPUs to get
potentially pending interrupts serviced.
This
The emulated ARM SBSA UART is using level triggered IRQ semantics,
however the current VGIC can only handle edge triggered IRQs, really.
Disable the existing workaround for this problem in case we have the
new VGIC in place, which can properly handle level triggered IRQs.
Signed-off-by: Andre Przy
The target register handlers are v2 emulation specific, so their
implementation lives entirely in vgic-mmio-v2.c.
We copy the old VGIC behaviour of assigning an IRQ to the first VCPU
set in the target mask instead of making it possibly pending on
multiple VCPUs.
This is based on Linux commit 2c234
The new VGIC implementation centers around a struct vgic_irq instance
per virtual IRQ.
Provide a function to retrieve the right instance for a given IRQ
number and (in case of private interrupts) the right VCPU.
This also includes the corresponding put function, which does nothing
for private inter
The VGIC model used for a domain (GICv2 or GICv3) determines the maximum
number of VCPUs for that guest, as GICv2 can only handle 8 processors.
In the moment we carry this per-VGIC-model limit in the vgic_ops,
alongside the model specific functions. That makes some sense, but
exposes some current V
The prototype for gic_remove_from_lr_pending() is the last function in
gic.h which references a VGIC data structure.
Move it over to vgic.h, so that we can remove the inclusion of vgic.h
from gic.h. We add it to asm/domain.h instead, where it is actually
needed.
Signed-off-by: Andre Przywara
---
Implement the framework for syncing IRQs between our emulation and the
list registers, which represent the guest's view of IRQs.
This is done in kvm_vgic_flush_hwstate and kvm_vgic_sync_hwstate, which
gets called on guest entry and exit.
The code talking to the actual GICv2/v3 hardware is added in
Processing maintenance interrupts and accessing the list registers
are dependent on the host's GIC version.
Introduce vgic-v2.c to contain GICv2 specific functions.
Implement the GICv2 specific code for syncing the emulation state
into the VGIC registers.
This also adds the hook to let Xen setup th
Add a new header file for the new and improved GIC implementation.
The big change is that we now have a struct vgic_irq per IRQ instead
of spreading all the information over various bitmaps in the ranks.
We include this new header conditionally from within the old header
file for the time being to
When playing around with hardware mapped, level triggered virtual IRQs,
there is the need to explicitly set the active state of an interrupt at
some point in time.
To prepare the GIC for that, we introduce a set_active_state() function
to let the VGIC manipulate the state of an associated hardware
The new VGIC will need to know the hypervisor base address at some
point, which is private to the hardware facing part of the VGIC so far.
Add a parameter to vgic_v2_setup_hw() to pass this address on, so a VGIC
implementation can make use of it.
The current VGIC ignores this new parameter.
TODO:
Add an MMIO handling framework to the VGIC emulation:
Each register is described by its offset, size (or number of bits per
IRQ, if applicable) and the read/write handler functions. We provide
initialization macros to describe each GIC register later easily.
Separate dispatch functions for read an
Instead of hard coding the architected redistributor stride into the
code, lets use a clear #define to the two values for GICv3 and GICv4 and
clarify the algorithm to determine the needed stride value.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v3.c | 18 ++
x
This patch allocates and initializes the data structures used to model
the vgic distributor and virtual cpu interfaces. At that stage the
number of IRQs and number of virtual CPUs is frozen.
This is based on Linux commit ad275b8bb1e6, written by Eric Auger.
Signed-off-by: Andre Przywara
---
xen
The active register handlers are shared between the v2 and v3 emulation,
so their implementation goes into vgic-mmio.c, to be easily referenced
from the v3 emulation as well later.
Since activation/deactivation of an interrupt may happen entirely in the
guest without it ever exiting, we need some e
As the enable register handlers are shared between the v2 and v3
emulation, their implementation goes into vgic-mmio.c, to be easily
referenced from the v3 emulation as well later.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +-
xen/arch/arm/vgic/vgic-mmio.c| 114
As this register is v2 specific, its implementation lives entirely
in vgic-mmio-v2.c.
This register allows setting the source mask of an IPI.
This is based on Linux commit ed40213ef9b0, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 77 ++
To find an unused virtual IRQ number Xen uses a scheme to track used
virtual IRQs.
Implement this interface in the new VGIC to make the Xen core/arch code
happy.
This is actually somewhat VGIC agnostic, so is mostly a copy of the code
from the old VGIC. But it has to live in the VGIC files, so we c
Provide a vgic_queue_irq_unlock() function which decides whether a
given IRQ needs to be queued to a VCPU's ap_list.
This should be called whenever an IRQ becomes pending or enabled,
either as a result of a hardware IRQ injection, from devices emulated by
Xen (like the architected timer) or from MM
Currently vgic.h both contains prototypes used by Xen arch code outside
of the actual VGIC (for instance vgic_vcpu_inject_irq()), and prototypes
for functions used by the VGIC internally.
Group them to later allow an easy split with one #ifdef.
Signed-off-by: Andre Przywara
---
xen/include/asm-a
The Xen core/arch code relies on two abstracted functions to inject an
event channel IRQ and to query its pending state.
Implement those to query the state of the new VGIC implementation.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 20
1 file changed, 20 ins
At the moment we allocate exactly one page for struct vcpu on ARM, also
have a check in place to prevent it growing beyond 4KB.
As the struct includes the state of all 32 private (per-VCPU) interrupts,
we are at 3840 bytes on arm64 at the moment already. Growing the per-IRQ
VGIC structure even slig
Tell Xen whether a particular VCPU has an IRQ that needs handling
in the guest. This is used to decide whether a VCPU is runnable.
This is based on Linux commit 90eee56c5f90, written by Eric Auger.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic.c | 32
Triggering an IPI via this register is v2 specific, so the
implementation lives entirely in vgic-mmio-v2.c.
This is based on Linux commit 55cc01fb9004, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 47 +++-
1
Create vgic-mmio-v2.c to describe GICv2 emulation specific handlers
using the initializer macros provided by the VGIC MMIO framework.
Provide a function to register the GICv2 distributor registers to
the Xen MMIO framework.
The actual handler functions are still stubs in this patch.
This is based
Adds the sorting function to cover the case where you have more IRQs
to consider than you have LRs. We consider their priorities.
This pulls in Linux' list_sort.c , which is a merge sort implementation
for linked lists.
This is based on Linux commit 8e4447457965, written by Christoffer Dall.
Sign
When creating a GICv3 devicetree node, we currently insert the
redistributor-stride and #redistributor-regions properties, with fixed
values which are actually the architected ones. But those properties are
optional and only needed to cover for broken platforms, where the values
differ from the arc
map_resources is the last initialization step needed before the first
VCPU is run. At that stage the code stores the MMIO base addresses used.
Also it registers the respective register frames with the MMIO framework.
This is based on Linux commit cbae53e663ea, written by Eric Auger.
Signed-off-by
Now that we have both the old VGIC prepared to cope with a sibling and
the code for the new VGIC in place, lets add a Kconfig option to enable
the new code and wire it into the Xen build system.
This will add a compile time option to use either the "old" or the "new"
VGIC.
In the moment this is res
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