On 27/08/2019 17:45, Andrew Cooper wrote:
> AMD explicitly doesn't have leaf 4. Their leaf 0x801d is similar in
> behaviour (by having subleafs), and is mostly compatible, but
> irritatingly doesn't have an identical data layout.
>
> I've got another query out with AMD because the documentatio
On 27/08/2019 16:08, Jan Beulich wrote:
> On 27.08.2019 16:47, Andrew Cooper wrote:
>> On 01/07/2019 12:56, Jan Beulich wrote:
>>> --- a/xen/arch/x86/pv/emul-priv-op.c
>>> +++ b/xen/arch/x86/pv/emul-priv-op.c
>>> @@ -1121,7 +1121,7 @@ static int write_msr(unsigned int reg, u
>>> @@ -1130,6 +1130,8
On 27.08.2019 16:47, Andrew Cooper wrote:
On 01/07/2019 12:56, Jan Beulich wrote:
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -1121,7 +1121,7 @@ static int write_msr(unsigned int reg, u
@@ -1130,6 +1130,8 @@ static int cache_op(enum x86emul_cache_o
*
On 01/07/2019 12:56, Jan Beulich wrote:
> Rev 035 of Intel's ISA extensions document does not state intercept
> behavior for the insn (I've been in-officially told that the distinction
unofficially.
> is going to be by exit qualification, as I would have assumed
> considering that this way it's s
> -Original Message-
> From: Jan Beulich
> Sent: 01 July 2019 12:57
> To: xen-devel@lists.xenproject.org
> Cc: Andrew Cooper ; Paul Durrant
> ; Roger Pau Monne
> ; Wei Liu
> Subject: [PATCH 2/6] x86emul: support WBNOINVD
>
> Rev 035 of Intel's ISA extensions document does not state inte
