On 2025/2/5 18:40, Jan Beulich wrote:
> On 05.02.2025 11:31, Chen, Jiqian wrote:
>> On 2025/2/5 17:58, Jan Beulich wrote:
>>> On 05.02.2025 10:12, Chen, Jiqian wrote:
On 2025/2/5 16:56, Roger Pau Monné wrote:
> On Wed, Feb 05, 2025 at 03:42:30AM +, Chen, Jiqian wrote:
>> On 2025/1/
On 05.02.2025 11:31, Chen, Jiqian wrote:
> On 2025/2/5 17:58, Jan Beulich wrote:
>> On 05.02.2025 10:12, Chen, Jiqian wrote:
>>> On 2025/2/5 16:56, Roger Pau Monné wrote:
On Wed, Feb 05, 2025 at 03:42:30AM +, Chen, Jiqian wrote:
> On 2025/1/27 23:08, Roger Pau Monné wrote:
>> On Mo
On 2025/2/5 17:58, Jan Beulich wrote:
> On 05.02.2025 10:12, Chen, Jiqian wrote:
>> On 2025/2/5 16:56, Roger Pau Monné wrote:
>>> On Wed, Feb 05, 2025 at 03:42:30AM +, Chen, Jiqian wrote:
On 2025/1/27 23:08, Roger Pau Monné wrote:
> On Mon, Jan 27, 2025 at 03:52:31PM +0100, Jan Beulich
On 05.02.2025 10:12, Chen, Jiqian wrote:
> On 2025/2/5 16:56, Roger Pau Monné wrote:
>> On Wed, Feb 05, 2025 at 03:42:30AM +, Chen, Jiqian wrote:
>>> On 2025/1/27 23:08, Roger Pau Monné wrote:
On Mon, Jan 27, 2025 at 03:52:31PM +0100, Jan Beulich wrote:
> On 27.01.2025 15:41, Roger Pau
On 2025/2/5 16:56, Roger Pau Monné wrote:
> On Wed, Feb 05, 2025 at 03:42:30AM +, Chen, Jiqian wrote:
>> On 2025/1/27 23:08, Roger Pau Monné wrote:
>>> On Mon, Jan 27, 2025 at 03:52:31PM +0100, Jan Beulich wrote:
On 27.01.2025 15:41, Roger Pau Monné wrote:
> On Mon, Jan 27, 2025 at 03:
On Wed, Feb 05, 2025 at 03:42:30AM +, Chen, Jiqian wrote:
> On 2025/1/27 23:08, Roger Pau Monné wrote:
> > On Mon, Jan 27, 2025 at 03:52:31PM +0100, Jan Beulich wrote:
> >> On 27.01.2025 15:41, Roger Pau Monné wrote:
> >>> On Mon, Jan 27, 2025 at 03:20:40PM +0100, Jan Beulich wrote:
> On 2
On 2025/1/27 22:52, Jan Beulich wrote:
> On 27.01.2025 15:41, Roger Pau Monné wrote:
>> On Mon, Jan 27, 2025 at 03:20:40PM +0100, Jan Beulich wrote:
>>> On 23.01.2025 04:50, Jiqian Chen wrote:
v5->v6 changes:
* Changed "1UL" to "1ULL" in PCI_REBAR_CTRL_SIZE idefinition for 32 bit
ar
On 2025/1/27 23:08, Roger Pau Monné wrote:
> On Mon, Jan 27, 2025 at 03:52:31PM +0100, Jan Beulich wrote:
>> On 27.01.2025 15:41, Roger Pau Monné wrote:
>>> On Mon, Jan 27, 2025 at 03:20:40PM +0100, Jan Beulich wrote:
On 23.01.2025 04:50, Jiqian Chen wrote:
> v5->v6 changes:
> * Change
On Mon, Jan 27, 2025 at 03:52:31PM +0100, Jan Beulich wrote:
> On 27.01.2025 15:41, Roger Pau Monné wrote:
> > On Mon, Jan 27, 2025 at 03:20:40PM +0100, Jan Beulich wrote:
> >> On 23.01.2025 04:50, Jiqian Chen wrote:
> >>> v5->v6 changes:
> >>> * Changed "1UL" to "1ULL" in PCI_REBAR_CTRL_SIZE idefi
On 27.01.2025 15:41, Roger Pau Monné wrote:
> On Mon, Jan 27, 2025 at 03:20:40PM +0100, Jan Beulich wrote:
>> On 23.01.2025 04:50, Jiqian Chen wrote:
>>> v5->v6 changes:
>>> * Changed "1UL" to "1ULL" in PCI_REBAR_CTRL_SIZE idefinition for 32 bit
>>> architecture.
>>> * In rebar_ctrl_write used "ba
On Mon, Jan 27, 2025 at 03:20:40PM +0100, Jan Beulich wrote:
> On 23.01.2025 04:50, Jiqian Chen wrote:
> > v5->v6 changes:
> > * Changed "1UL" to "1ULL" in PCI_REBAR_CTRL_SIZE idefinition for 32 bit
> > architecture.
> > * In rebar_ctrl_write used "bar - pdev->vpci->header.bars" to get index
> >
On 23.01.2025 04:50, Jiqian Chen wrote:
> v5->v6 changes:
> * Changed "1UL" to "1ULL" in PCI_REBAR_CTRL_SIZE idefinition for 32 bit
> architecture.
> * In rebar_ctrl_write used "bar - pdev->vpci->header.bars" to get index
> instead of reading
> from register.
> * Added the index of BAR to error
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