Michael!
On Thu, Apr 27 2023 at 14:48, Michael Kelley wrote:
> From: Thomas Gleixner Sent: Friday, April 14, 2023 4:44
> PM
>
> I smoke-tested several Linux guest configurations running on Hyper-V,
> using the "kernel/git/tglx/devel.git hotplug" tree as updated on April 26th.
> No functional iss
From: Thomas Gleixner Sent: Friday, April 14, 2023 4:44 PM
[snip]
>
> Conclusion
> --
>
> Adding the basic parallel bringup mechanism as provided by this series
> makes a lot of sense. Improving particular issues as pointed out in the
> analysis makes sense too.
>
> But trying to solv
On Thu, Apr 20 2023 at 17:57, Thomas Gleixner wrote:
> On Thu, Apr 20 2023 at 07:51, Sean Christopherson wrote:
> Something like the completely untested below should just work whatever
> APIC ID the BIOS decided to dice.
>
> That might just work on SEV too without that GHCB muck, but what do I
> kn
Dear Thomas,
Am 20.04.23 um 21:10 schrieb Thomas Gleixner:
On Thu, Apr 20 2023 at 18:47, Paul Menzel wrote:
Am 20.04.23 um 17:57 schrieb Thomas Gleixner:
I quickly applied it on top of your branch, but I am getting:
As I said it was untested. I was traveling and did not have access to a
mach
On Thu, Apr 20 2023 at 21:10, Thomas Gleixner wrote:
> On Thu, Apr 20 2023 at 18:47, Paul Menzel wrote:
>> Am 20.04.23 um 17:57 schrieb Thomas Gleixner:
>> I quickly applied it on top of your branch, but I am getting:
>
> As I said it was untested. I was traveling and did not have access to a
> mac
On Thu, Apr 20 2023 at 18:47, Paul Menzel wrote:
> Am 20.04.23 um 17:57 schrieb Thomas Gleixner:
> I quickly applied it on top of your branch, but I am getting:
As I said it was untested. I was traveling and did not have access to a
machine to even build it completely. Fixed up and tested version
Dear Thomas,
Am 20.04.23 um 17:57 schrieb Thomas Gleixner:
On Thu, Apr 20 2023 at 07:51, Sean Christopherson wrote:
On Thu, Apr 20, 2023, Thomas Gleixner wrote:
On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote:
On 20/04/2023 9:32 am, Thomas Gleixner wrote:
On Wed, Apr 19, 2023, Andrew Coop
On Thu, Apr 20 2023 at 07:51, Sean Christopherson wrote:
> On Thu, Apr 20, 2023, Thomas Gleixner wrote:
>> On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote:
>> > On 20/04/2023 9:32 am, Thomas Gleixner wrote:
>> > > On Wed, Apr 19, 2023, Andrew Cooper wrote:
>> > > > This was changed in x2APIC, whi
On Thu, Apr 20, 2023, Thomas Gleixner wrote:
> On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote:
> > On 20/04/2023 9:32 am, Thomas Gleixner wrote:
> > > On Wed, Apr 19, 2023, Andrew Cooper wrote:
> > > > This was changed in x2APIC, which made the x2APIC_ID immutable.
>
> >> I'm pondering to simply
On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote:
> On 20/04/2023 9:32 am, Thomas Gleixner wrote:
>> I'm pondering to simply deny parallel mode if x2APIC is not there.
>
> I'm not sure if that will help much.
Spoilsport.
> Just because x2APIC is there doesn't mean it's in use. There are
> sever
On 20/04/2023 9:32 am, Thomas Gleixner wrote:
> On Wed, Apr 19 2023 at 17:21, Andrew Cooper wrote:
>> On 19/04/2023 2:50 pm, Andrew Cooper wrote:
>> For xAPIC, the APIC_ID register is writeable (at least, model
>> specifically), and CPUID is only the value it would have had at reset.
>> So the AP
On Wed, Apr 19 2023 at 17:21, Andrew Cooper wrote:
> On 19/04/2023 2:50 pm, Andrew Cooper wrote:
>> What I'm confused by is why this system boots in the first place. I can
>> only think that's is a system which only has 4-bit APIC IDs, and happens
>> to function when bit 4 gets truncated off the t
Dear Thomas,
Am 19.04.23 um 14:38 schrieb Thomas Gleixner:
On Wed, Apr 19 2023 at 11:38, Thomas Gleixner wrote:
On Tue, Apr 18 2023 at 22:10, Paul Menzel wrote:
Am 18.04.23 um 10:40 schrieb Thomas Gleixner:
Can you please provide the output of cpuid?
Of course. Here the top, and the whole
On 19/04/2023 2:50 pm, Andrew Cooper wrote:
> On 19/04/2023 2:43 pm, Thomas Gleixner wrote:
>> On Wed, Apr 19 2023 at 14:38, Thomas Gleixner wrote:
>>> On Wed, Apr 19 2023 at 11:38, Thomas Gleixner wrote:
>>> IOW, the BIOS assignes random numbers to the AP APICs for whatever
>>> raisins, which leav
On 19/04/2023 2:43 pm, Thomas Gleixner wrote:
> On Wed, Apr 19 2023 at 14:38, Thomas Gleixner wrote:
>> On Wed, Apr 19 2023 at 11:38, Thomas Gleixner wrote:
>> IOW, the BIOS assignes random numbers to the AP APICs for whatever
>> raisins, which leaves the parallel startup low level code up a creek
On Wed, Apr 19 2023 at 14:38, Thomas Gleixner wrote:
> On Wed, Apr 19 2023 at 11:38, Thomas Gleixner wrote:
> IOW, the BIOS assignes random numbers to the AP APICs for whatever
> raisins, which leaves the parallel startup low level code up a creek
> without a paddle, except for actually reading the
On Wed, 2023-04-19 at 14:38 +0200, Thomas Gleixner wrote:
>
> I'm leaning towards disabling the CPUID lead 0x01 based discovery and be
> done with it.
Makes sense. The large machines where users really want the parallel
startup all ought to have X2APIC and hence CPUID 0x0b.
smime.p7s
Descripti
On Wed, Apr 19 2023 at 11:38, Thomas Gleixner wrote:
> On Tue, Apr 18 2023 at 22:10, Paul Menzel wrote:
>> Am 18.04.23 um 10:40 schrieb Thomas Gleixner:
>>> Can you please provide the output of cpuid?
>>
>> Of course. Here the top, and the whole output is attached.
>
> Thanks for the data. Can you
Paul!
On Tue, Apr 18 2023 at 22:10, Paul Menzel wrote:
> Am 18.04.23 um 10:40 schrieb Thomas Gleixner:
>> Can you please provide the output of cpuid?
>
> Of course. Here the top, and the whole output is attached.
Thanks for the data. Can you please apply the debug patch below and
provide the dmes
Dear Thomas,
Am 18.04.23 um 10:40 schrieb Thomas Gleixner:
On Tue, Apr 18 2023 at 08:58, Thomas Gleixner wrote:
On Mon, Apr 17 2023 at 19:40, Paul Menzel wrote:
Am 17.04.23 um 16:48 schrieb Thomas Gleixner:
On Mon, Apr 17 2023 at 13:19, Paul Menzel wrote:
Am 15.04.23 um 01:44 schrieb Thoma
On Tue, Apr 18 2023 at 08:58, Thomas Gleixner wrote:
> On Mon, Apr 17 2023 at 19:40, Paul Menzel wrote:
>> Am 17.04.23 um 16:48 schrieb Thomas Gleixner:
>>
>>> On Mon, Apr 17 2023 at 13:19, Paul Menzel wrote:
Am 15.04.23 um 01:44 schrieb Thomas Gleixner:
[0.258193] smpboot: CPU0: AMD
Paul!
On Mon, Apr 17 2023 at 19:40, Paul Menzel wrote:
> Am 17.04.23 um 16:48 schrieb Thomas Gleixner:
>
>> On Mon, Apr 17 2023 at 13:19, Paul Menzel wrote:
>>> Am 15.04.23 um 01:44 schrieb Thomas Gleixner:
>>> [0.258193] smpboot: CPU0: AMD A6-6400K APU with Radeon(tm) HD
>>> Graphics (family:
Dear Thomas,
Am 17.04.23 um 16:48 schrieb Thomas Gleixner:
On Mon, Apr 17 2023 at 13:19, Paul Menzel wrote:
Am 15.04.23 um 01:44 schrieb Thomas Gleixner:
[0.258193] smpboot: CPU0: AMD A6-6400K APU with Radeon(tm) HD
Graphics (family: 0x15, model: 0x13, stepping: 0x1)
[…]
[0.259329] sm
Paul!
On Mon, Apr 17 2023 at 13:19, Paul Menzel wrote:
> Am 15.04.23 um 01:44 schrieb Thomas Gleixner:
> [0.258193] smpboot: CPU0: AMD A6-6400K APU with Radeon(tm) HD
> Graphics (family: 0x15, model: 0x13, stepping: 0x1)
> […]
> [0.259329] smp: Bringing up secondary CPUs ...
> [0.2595
[Correct David’s address]
Am 17.04.23 um 13:19 schrieb Paul Menzel:
Dear Thomas,
Am 15.04.23 um 01:44 schrieb Thomas Gleixner:
This is a complete rework of the parallel bringup patch series (V17)
https://lore.kernel.org/lkml/20230328195758.1049469-1-usama.a...@bytedance.com
to addre
Dear Thomas,
Am 15.04.23 um 01:44 schrieb Thomas Gleixner:
This is a complete rework of the parallel bringup patch series (V17)
https://lore.kernel.org/lkml/20230328195758.1049469-1-usama.a...@bytedance.com
to address the issues which were discovered in review:
[…]
Thank you very mu
On 17/04/2023 11:30 am, Peter Zijlstra wrote:
> On Sat, Apr 15, 2023 at 01:44:13AM +0200, Thomas Gleixner wrote:
>
>> Background
>> --
>>
>> The reason why people are interested in parallel bringup is to shorten
>> the (kexec) reboot time of cloud servers to reduce the downtime of the
>> VM
On Sat, Apr 15, 2023 at 01:44:13AM +0200, Thomas Gleixner wrote:
> Background
> --
>
> The reason why people are interested in parallel bringup is to shorten
> the (kexec) reboot time of cloud servers to reduce the downtime of the
> VM tenants. There are obviously other interesting use ca
On 15.04.23 01:44, Thomas Gleixner wrote:
Hi!
This is a complete rework of the parallel bringup patch series (V17)
https://lore.kernel.org/lkml/20230328195758.1049469-1-usama.a...@bytedance.com
to address the issues which were discovered in review:
1) The X86 microcode loader serializ
Hi!
This is a complete rework of the parallel bringup patch series (V17)
https://lore.kernel.org/lkml/20230328195758.1049469-1-usama.a...@bytedance.com
to address the issues which were discovered in review:
1) The X86 microcode loader serialization requirement
https://lore.kernel.org
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