>>> On 30.10.18 at 12:00, wrote:
> On Mon, Oct 29, 2018 at 08:19:20AM -0600, Jan Beulich wrote:
>> >>> On 19.10.18 at 17:20, wrote:
>> > --- a/xen/arch/x86/hvm/svm/svm.c
>> > +++ b/xen/arch/x86/hvm/svm/svm.c
>> > @@ -1272,6 +1272,24 @@ void svm_host_osvw_init()
>> > spin_unlock(&osvw_lock);
On Mon, Oct 29, 2018 at 08:19:20AM -0600, Jan Beulich wrote:
> >>> On 19.10.18 at 17:20, wrote:
> > --- a/xen/arch/x86/hvm/svm/svm.c
> > +++ b/xen/arch/x86/hvm/svm/svm.c
> > @@ -1272,6 +1272,24 @@ void svm_host_osvw_init()
> > spin_unlock(&osvw_lock);
> > }
> >
> > +static int acpi_c1e_qui
>>> On 19.10.18 at 17:20, wrote:
> --- a/xen/arch/x86/hvm/svm/svm.c
> +++ b/xen/arch/x86/hvm/svm/svm.c
> @@ -1272,6 +1272,24 @@ void svm_host_osvw_init()
> spin_unlock(&osvw_lock);
> }
>
> +static int acpi_c1e_quirk(int dir, unsigned int port, unsigned int bytes,
> +
On Fri, Oct 19, 2018 at 04:20:21PM +0100, Roger Pau Monne wrote:
> PV Dom0 has a quirk for some AMD processors, where enabling ACPI can
> also enable C1E mode. Apply the same workaround as done on PV for a
> PVH Dom0, which consist on trapping accesses to the SMI command IO
> port and disabling C1E
PV Dom0 has a quirk for some AMD processors, where enabling ACPI can
also enable C1E mode. Apply the same workaround as done on PV for a
PVH Dom0, which consist on trapping accesses to the SMI command IO
port and disabling C1E if ACPI is enabled.
Reported-by: Jan Beulich
Signed-off-by: Roger Pau
