Re: [Xen-devel] [PATCH RFC v2 10/10] AMD/IOMMU: correct IRTE updating

2019-07-03 Thread Jan Beulich
On 02.07.2019 17:08, Andrew Cooper wrote: > On 27/06/2019 16:23, Jan Beulich wrote: >> While for 32-bit IRTEs I think we can safely continue to assume that the >> writes will translate to a single MOV, the use of CMPXCHG16B is more > > The CMPXCHG16B here is stale. Indeed, as is the 32-bit IRTE p

Re: [Xen-devel] [PATCH RFC v2 10/10] AMD/IOMMU: correct IRTE updating

2019-07-02 Thread Andrew Cooper
On 27/06/2019 16:23, Jan Beulich wrote: > While for 32-bit IRTEs I think we can safely continue to assume that the > writes will translate to a single MOV, the use of CMPXCHG16B is more The CMPXCHG16B here is stale. > heavy handed than necessary for the 128-bit form, and the flushing > didn't get

[Xen-devel] [PATCH RFC v2 10/10] AMD/IOMMU: correct IRTE updating

2019-06-27 Thread Jan Beulich
While for 32-bit IRTEs I think we can safely continue to assume that the writes will translate to a single MOV, the use of CMPXCHG16B is more heavy handed than necessary for the 128-bit form, and the flushing didn't get done along the lines of what the specification says. Mark entries to be updated